Sampada J. — DevOps Engineer

TECHNICAL SKILL SET:- 🔹HDL : Verilog 🔹HDVL : System Verilog 🔹Verification Methodology : UVM 🔹Knowledge : RTL coding, FSM based design, Basics of Static Timing Analysis concepts, Clock domain crossing basic concepts, Code coverage, Functional coverage, Waveform debug, Simulation. 🔹Simulation tools : VCS - Synopsys, QuestaSim, ModelSim - Mentor Graphics, Riviera Pro- Aldec, Xcelium- Cadence. 🔹Protocols : DDR-5, AMBA 3 AXI, AHB-Lite, APB, AHB- APB bridge controller

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in RTL and Functional Verification.

Location: Bengaluru, Karnataka, India

Experience: 7 yrs 2 mos