Sardar Harpreeth Singh

Software Engineer

Bangalore Urban, Karnataka, India9 yrs experience
Most Likely To SwitchHighly Stable

Key Highlights

  • 7+ years in VLSI semiconductor industry
  • Expertise in Physical Design and Verification
  • Experience with advanced technology nodes
Stackforce AI infers this person is a VLSI Physical Design Engineer with extensive experience in semiconductor technology.

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Skills

Core Skills

Physical DesignStatic Timing Analysis

Other Skills

Crosstalk AnalysisPower IR/EMPhysical VerificationVery-Large-Scale Integration (VLSI)vlsi design and verificationRTL DesignRTL VerificationVerilogmodel simquesta simgvim editorAnalog layoutFunctional VerificationApplication-Specific Integrated Circuits (ASIC)Logic Synthesis

About

B.Tech in Electronics & communication with 7+ years of strong experience in VLSI semiconductor industry Physical Design & physical verification. > Expertise in Physical Design activities such as : Floor-planning, P&R, Extraction, Power IR/EM, Physical Verification (DRC/LVS) and Signal Integrity > Advanced knowledge of place and route methodologies > understanding on aspects of Physical design trending from Synthesis to signoff. > Worked on TSMC lower technology nodes 2nm , 3nm, 5nm, 7nm, 10nm & 14nm & Intel technology nodes 18A. > Static Timing/Crosstalk Analysis and timing closure > Physical Design Flow and Methodology > Ability to lead the team along with the project execution > Expertise with Backend Tools (ICC, PrimeTime, Redhawk , Redhawk_sc, ICV & ICWBEV ) > programming knowledge in TCL Scripting, AWK, grep, sed & Unix. > Experience in working with analog IP, hard and soft macros and delivering hierarchical design projects > Communicate regularly with the implementation and project team to resolve issues. > I have worked on block section and super section level hierarchy. > Worked on varieties of ECO's which would involve calibre, timing and RV fixes > Worked on block, section and super section level.

Experience

9 yrs
Total Experience
2 yrs 3 mos
Average Tenure
3 yrs 9 mos
Current Experience

Intel corporation

Physical Design Engineer

Jul 2022Present · 3 yrs 9 mos · Bengaluru, Karnataka, India

Physical DesignStatic Timing AnalysisCrosstalk AnalysisPower IR/EMPhysical Verification

Ulkasemi limited

Senior Physical Design Engineer

Jul 2021Jul 2022 · 1 yr · Bengaluru, Karnataka, India

  • SOC design Engineer

Capgemini

2 roles

Senior Physical Design Engineer

Promoted

Jan 2019Jul 2021 · 2 yrs 6 mos

Design Engineer

Jan 2018Jan 2019 · 1 yr

Jagruti institute

Internship Trainee

Mar 2017Dec 2017 · 9 mos · Hyderabad, Telangana, India

  • certification with Hands on training in VLSI domain, Physical design

Education

Jawaharlal Nehru Technological University

Bachelor of Technology - BTech

Jan 2012Jan 2016

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