Surojit Halder

Software Engineer

Kolkata, West Bengal, India7 yrs 10 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in RTL design and digital verification.
Proficient in multiple serial protocols including I2C and SPI.
Strong background in power analysis and optimization.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in RTL and digital verification.

Contact

s.elex.h@gmail.com LinkedIn

Skills

Core Skills

Rtl DesignDigital DesignDigital Design Verification

Other Skills

Cadence toolsCore JavaDDR4DDR5DRAM architecturesDebuggingDigital DesignsDigital VLSIFinesimLinuxMatlabOptical TransmissionPython (Programming Language)RTL DevelopmentSDH/SONET

About

Currently, I am working in RTL design domain as an Senior Digital Design Engineer in Texas Instruments. Expertise in DDR/LPDDR, SPI, I2C, RTL design, System Verilog, UVM, Cadence tools, Finesim, Python & Linux. I have completed M.Tech in Microelectronics & VLSI from IIT Kharagpur.

Experience

Texas instruments

Senior Digital Design Engineer

May 2022 – Present · 3 yrs 10 mos · Bengaluru, Karnataka, India · On-site

Handled end to end digital design cycle from design to physical design
Developed RTL to optimize the design to achieve best power, performance, and area.
Handled of digital synthesis, place and route, STA and DFT
Collaborate with cross-functional teams to define specifications
Experienced in identifying and implementing complex ECO in netlist.
Experienced with power analysis, IR drop measurement, power planning
Experienced with common serial protocols such as I2C, SPI

RTL DesignDigital DesignsRTL DevelopmentCadence toolsSystem VerilogUVM+5

Micron technology

Associate Engineer

Nov 2020 – May 2022 · 1 yr 6 mos · Hyderabad, Telangana, India

Provided verification support to design projects by simulating, analyzing and debugging pre-silicon chip designs.
Developed patterns and regressions to increase the functional coverage for all DRAM architectures and features.
Developed and maintained UVM test benches and test vectors.

UVMSimulationDebuggingDRAM architecturesDigital Design verification

Indian institute of technology, kharagpur

Teaching Assistant

Jul 2019 – Mar 2020 · 8 mos · Kharagpur I, India

Providing support to the professor to grade the students & monitoring quizzes.
Working on following undergraduate course Semiconductor Device Modeling (EC60201), Basic Electronics Lab (EC29001) & Analog Circuit Lab(EC29008) .
Provide guidance to the undergraduate students in the basic electronics and Analog circuit Laboratory.

Ericsson

Assistant Engineer

Oct 2015 – Aug 2017 · 1 yr 10 mos · Noida, Uttar Pradesh, India

Responsible for Installation, Disconnection, Migration, Traffic Testing & maintenance of DS1, DS3 & above SDH/SONET Facility as an Entrance provisioner.
Up-gradation of bandwidth and migration Ethernet Lines.
Tower roll migration with Ericsson field tech and LEC.
Co-coordinating with field engineers, other groups to resolve data network-related problems on a daily basis.
Update and Upgrade of BTS, Node B and eNode B Networks.
Troubleshooting in BSC and BTS.