Nitin Gupta — Software Engineer
Expertise : System Verilog, UVM, system Verilog/UVM based SOC Verification, Gate level simulation(GLS), Mixed-signal verification, AMS, IP/Subsystem level Verification Formal Verification(Jasper Gold),IP/subsystem level verification , Functional safety expert , DDR- PHY. Specialties: System Verilog, Verilog, Video Protocols,UVM,SPI,I2C,AMBA protocols, JTAG
Stackforce AI infers this person is a VLSI Verification Engineer with expertise in SOC and Mixed-signal domains.
Experience: 12 yrs 5 mos
Career Highlights
- Expert in System Verilog and UVM-based SOC Verification.
- Proficient in Mixed-signal and Gate level simulation.
- Functional safety expert with extensive verification experience.
Work Experience
Renesas Electronics
Senior Design Verification Engineer (3 yrs 2 mos)
Intel Corporation
Design Verification Engineer (11 mos)
ST Microelectronics
Verification Engineer (4 yrs 7 mos)
HCL Technologies
Lead Engineer (1 yr 11 mos)
MTS (1 yr 9 mos)
Education
VLSI at Thapar Institute of Engineering & Technology
