Ankur Vaish

Director of Engineering

Bengaluru, Karnataka, India15 yrs 11 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 15 years of design verification experience.
Expertise in PCIe Protocol from Gen 1 to Gen 6.
Proven leadership in managing verification teams.

Stackforce AI infers this person is a semiconductor verification expert with extensive experience in PCIe and system-level verification.

Contact

nkr_vsh@yahoo.com LinkedIn

Skills

Core Skills

Design VerificationTeam ManagementPcie Protocol VerificationTeam LeadershipVerification LeadershipSystem Level VerificationDevice Driver Development

Other Skills

ARMASICApplication-Specific Integrated Circuits (ASIC)CC++Computer ArchitectureDebuggingDevice DriversDigital DesignEDAEmbedded SystemsEmulationFPGAFunctional VerificationIC

About

15+ years of Design verification experience with experience on architecting and developing constrained random coverage driven UVM based testbenches from scratch. Expertise in PCIe Protocol - Gen 1 to Gen 6 Experience in Managing/Leading Verification Teams. Experience on all level of Verification that includes IP Level Verification, Subsystem Level Verification and SoC level Verification. Experience in writing VIPs for Simulation as well as Emulation. Experience with UVM, Verilog/System Verilog, Synopsys/Mentor/Cadence tool sets. Experience on Leading multi-team and multi-site working environment.

Experience

Google

2 roles

Design Verification Manager, Security

Promoted

Sep 2023 – Present · 2 yrs 6 mos · Bengaluru, Karnataka, India · On-site

Leading/Managing the BLR Pixel/gChips Security DV Team.

Design VerificationTeam Management

Design Verification Lead, Security

Jun 2022 – Sep 2023 · 1 yr 3 mos · Bengaluru, Karnataka, India · On-site

Cadence design systems

PCIe IP Verification Lead

Jan 2021 – Jun 2022 · 1 yr 5 mos · Noida, Uttar Pradesh, India

Leading the verification effort to verify Gen 5/Gen 6 DLL Layer for Cadence's PCIe HPA Gen 5/Gen 6 IP

PCIe Protocol VerificationTeam Leadership

Mentor graphics

3 roles

PCIe Technical Lead

May 2019 – Jan 2021 · 1 yr 8 mos · Noida, Uttar Pradesh, India

Lead Member Technical Staff

Aug 2014 – Dec 2016 · 2 yrs 4 mos

Lead USB Transactor Team.
Lead HDMI Transactor Team.
Responsible for overall delivery of HDMI Transactor.
Responsible for Developing HDL (in Verilog) for HDMI Source as well as Sink.
Delivered AXI3 Transactor with Pure C HVL Environment. Successfully Deployed in Intel, Austin.
Worked on MIPI CSI-2 and MIPI DSI Transactors. Successfully Deployed in Samsung, Korea.

Senior Member Technical Staff

Jul 2012 – Jul 2014 · 2 yrs

I am involved in development of verification transactors of MIPI Protocols like DSI, D-Phy, CSI etc. for Emulation.

Qualcomm

Senior Lead Engineer

Dec 2016 – May 2019 · 2 yrs 5 mos · Noida, Uttar Pradesh, India

Verification Lead for PCIe DMA Bridge IP designed from scratch for Qualcomm’s AI Inference Chip (AI Cloud 100)
Worked with highly skilled verification team on couple of generation of ARM based Qualcomm Centriq server SoCs.
Integration & system level verification of ARM based System Memory Management Unit ( SMMU ) in PCIe Subsystem.
Development, maintenance and support of SMMU Verification IPs that can be picked by teams across geographies.
Development/maintenance of C based SMMU drivers for native environments.
Understanding of ARMv8 page tables and memory management.
Subsystem Verification Owner for Peripheral Subsystem (that includes peripheral IPs like USB 2.0, I2C, UART, SPI, etc.).
Did Verification of USB 2.0 and SMMU IPs present in Peripheral Subsystem at SoC Level.
Did Verification of all the Security Protection Units present in Qualcomm’s Server Chip at SoC Level.
Did Complete IP Verification and Code Coverage Closure for Scatter Gather DMA Module in completely random constraint UVM Environment
Mentored and trained new hires, experienced folks on Qualcomm flow and verification.

Verification LeadershipSystem Level Verification

Nvidia

ASIC Engineer

Jan 2011 – Jul 2012 · 1 yr 6 mos

I was involved in System Level Verification of HDMI, Video Encoder and Decoder, Display and Usecase Development for Nvidia's Tegra Chips.

St-ericsson

System Software Engineer

Aug 2010 – Jan 2011 · 5 mos

I was involved in development of kernal device drivers for sensors like Ambient Light Sensor, Accelerometer, Magnetometer, Proximity Sensor etc. for U8500 mobile platform and was also responsible for their interfacing with Android.

System Level Verification