Harshal Kalyane

CTO

Rotterdam, South Holland, Netherlands10 yrs 6 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in RTL Design and Verification Engineering.
Proven track record in coordinating complex design teams.
Strong background in Microelectronics and VLSI Design.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in RTL Design and Verification.

Contact

Skills

Core Skills

Rtl DesignVerification EngineeringEmbedded Systems

Other Skills

CCDC ValidationCSR validationCUDACadenceComputer ArchitectureDesign and Architecture coordinationIP connectivityIP ownershipLinuxMatlabMicrosoft ExcelMicrosoft OfficeMicrosoft WordNeuromorphic Computing

About

Experienced Placement Coordinator with a demonstrated history of working in the higher education industry. Skilled in Python, C++, Operating Systems, VLSI, FPGA, RTL Design and Teamwork. Strong community and social services professional with a Master of Technology (MTech) focused in Microelectronics and VLSI Design from Indian Institute of Technology, Bombay.

Experience

Rambus

Lead Member Of Technical Staff

Mar 2022 – Present · 4 yrs · Rotterdam, South Holland, Netherlands

Analog devices

Senior Design Verification Engineer

May 2019 – Mar 2022 · 2 yrs 10 mos · Greater Bengaluru Area

Intel corporation

SoC Design Engineer

Jul 2017 – May 2019 · 1 yr 10 mos · Bengaluru, Karnataka, India

Responsibilities include IP ownership, coordinating Design and Architecture teams at multiple sites, ensuring bug-free integration of IPs.
Experience of working on multiple projects and multiple blocks simultaneously, collaborating with multiple
teams and individuals.
Validation of Control Status and Functional registers of IPs at Sub-System Level.
{ Developed the test plan for CSR validation, Test plan includes all scenarios (Legal/ Illegal Access,
Attribute testing of registers from RAL and Accessibility on different Interfaces) and verified with
architect and IP owners. Written sequences (OVM and Intel proprietary OVM libraries (equivalent
to UVM)) to cover these scenarios.
Validation of Acceleration IP at Sub-System Level (Work in Progress)
{ Making sure of IP connectivity is proper at Sub-System Level, porting of IP functional sequences at
Sub-System to make sure that reusability of sequences at SoC.
Volume validation at Sub-System Level (Work in Progress).
{ Written mixer to run multiple function sequences and registers access sequences in parallel with a
large number of seeds.
Got many recognitions for finding bugs in IPs at Sub-System.
RDL integration of IPs at Sub-System, validation, and review of their quality with SoC architect.
CDC Validation for SubSystem

IP ownershipDesign and Architecture coordinationCSR validationTest plan developmentValidation of Acceleration IPVolume validation+4

Indian institute of technology, bombay

Company Coordinator, IITB Placement Cell

Apr 2016 – May 2017 · 1 yr 1 mo · Mumbai Metropolitan Region

Working with a Institute placement team of IIT Bombay, responsible for contacting and coordinating with organizations for recruitment of around 1600 final year students in IITB.
Identification of new potential recruiters and developing professional acquaintance with HR personnel of various Indian and foreign organizations
Coordination between placement cell and department placement coordinators in conducting & planning preparatory events such as workshop, tests and Pre-placement talks.

Whirlpool

Internship

Aug 2012 – May 2013 · 9 mos · Pune

Project was sponsored by Whirlpool.There I worked on Whirlpool Inter Device communication protocol, user interface design for PC application, PCB design and USB communication.