Pankaj Mudgil

CEO

Rohtak, Haryana, India7 yrs 10 mos experience
Most Likely To SwitchAI Enabled

Key Highlights

  • Led multiple product tape-outs at top tech companies.
  • Founded a trading firm focusing on algorithmic strategies.
  • Expertise in VLSI design and digital electronics.
Stackforce AI infers this person is a Semiconductor and Finance professional with expertise in VLSI design and algorithmic trading.

Contact

Skills

Core Skills

Go-to-market StrategyProduct OperationsDigital ElectronicsVery-large-scale Integration (vlsi)Algorithmic TradingEquity Research

Other Skills

5G ArchitectureAdministrationAlgorithmsAnalog Circuit DesignArtificial Intelligence/Machine LearningAutonomous CarsBig DataBloomberg PortalBusiness & Product ManagementBusiness DevelopmentCConcepts of GeographyCritical Chain Scheduling and ExecutionCritical Decision MakingData Analytics

About

• Full-time experience : Digital & Physical Design Implementation in 13 product tape-outs (3 at NXP Semiconductors, 4 at Qualcomm, 2 at Texas Instruments, 4 at Google) • Venture Experience : Product Lifecycle Planning & Management, Quantitative strategy development, Algorithmic trading, Software Development, Human resources planning, Business Development, Pre-Seed investments raising, Equity management, Financial Valuations • Interest - HFT, Hardware Design, Private Equity, Investment Banking, Quantitative Research, Finance, Business & Product Management, Social Development • Administration & Business Development : Governance, Political Science, Concepts of Geography, Historical Learning Implementation & Improvements, Critical Decision Making, Macro-Economics, Micro-Economics • Intermediate Business knowledge- Finance, Economics, Project Management, Risk Management, Six Sigma Process Implementation, Requirements Management & Traceability, Critical Chain Scheduling and Execution, HRM, and Portfolio Management, Lean Six Sigma, Investment methodologies & HFT. • Strong areas- Verilog Digital Design, VLSI Physical Design, Data Analytics, Programming in C, data structures (e.g. linked lists, graphs, structures), and algorithms (e.g. greedy, dynamic programming) • Basic technical knowledge- LLM Models, Artificial Intelligence/Machine Learning, Big Data, Hadoop, IoT, 5G Architecture, Wireless Communication, Satellite Communication, MySQL, Power BI, Autonomous Cars, Bloomberg Portal, Pro-Chain, Tableau, MATLAB, IoT, R for analytics.

Experience

7 yrs 10 mos
Total Experience
1 yr 7 mos
Average Tenure
3 yrs 6 mos
Current Experience

Google

4 roles

Product Manager

Jun 2025Present · 1 yr

  • Google Core - xEDA

Senior Consultant Strategy Operations

Promoted

Sep 2024Present · 1 yr 9 mos

  • Google Cloud CPDG & Pixel
Go-to-Market StrategyProduct OperationsOrganizational Consulting

Startup Success Manager

Jun 2023Oct 2023 · 4 mos

  • Google For Startups India - Venture Capital team

Silicon Physical Design Engineer

Dec 2022Present · 3 yrs 6 mos

  • Google Pixel - RTL to GDS Implementation

Texas instruments

Lead Digital Design Engineer

Feb 2022Dec 2022 · 10 mos · Bengaluru, Karnataka, India

  • Low Power Audio Amplifiers Group
  • RTL Design & Physical Implementation Engineer - Team lead, 2 product tape-outs.
Digital ElectronicsVery-Large-Scale Integration (VLSI)Analog Circuit DesignVerilogResearch and Development (R&D)Microsoft Office+6

Statsquant capital

Founder

Feb 2021Jun 2021 · 4 mos · New Delhi, Delhi, India

  • Trading firm focused on Equity Research and Algorithmic Trading in Indian markets
  • We focus on high alpha generating Quantitative Strategies
  • We are a team of curious engineers and statisticians who like to solve challenging problems.
  • Currently focusing on low latency trading system development and Machine Learning
  • Following robust risk management to develop strategies (Active in Cash, F&O, Fixed Income)
CMicrosoft OfficeLeadershipAlgorithmsMicrosoft ExcelAlgorithmic Trading+1

Qualcomm

STA Engineer

Nov 2020Feb 2022 · 1 yr 3 mos · Noida, Uttar Pradesh, India

  • 4 product tape-outs, PGV & STA Engineer
Digital ElectronicsVery-Large-Scale Integration (VLSI)VerilogMicrosoft OfficeSoCAlgorithms+2

Nxp semiconductors

2 roles

Senior Physical Design Engineer

Jan 2020Nov 2020 · 10 mos

  • Synthesis, CLP & PNR Engineer
Digital ElectronicsVery-Large-Scale Integration (VLSI)VerilogResearch and Development (R&D)Microsoft OfficeSoC+5

Digital Design & Architecture Engineer

Jul 2018Dec 2019 · 1 yr 5 mos

  • Digital Design:
  • Explored implementation of existing processors on RISC-V open architecture
  • Learnt ARM-based CPU architectures and instruction sets
  • Got good knowledge of NOC and ARM-based high-performance bus architecture
  • Learnt RTL design, linting checks, CDC, FIFO implementation, RDC, and basics of DFT, UVM Verification
  • Product Tapeout: TEF82xx -- Automotive industry’s first production-ready 4D Imaging Radar
  • Responsible for RTL to GDS physical hardening for Waveform generation,Rx,Tx,LO, SPI, LDO, bios
  • Performed PnR for top-level IP hardening with ILMs and scan netlists on MSOT design
  • Filed Invention Disclosure on Radar-based autonomous cars navigation
  • Received “Cheers for Peers award for excellence” within one year of experience
  • Received “Team Bravo Award” for smooth project execution
  • Non-Project :
  • Captained Business Line in NXP sports week (managed & captained 147 employees)
  • Formed 10 teams for 10 different sports (e.g. Cricket, Basketball, Table Tennis, etc.)
  • Responsible for finance for sports equipment kits, team t-shirts, grounds/courts booking
  • Responsible for team transportation, refreshments
  • Learnt project execution with Pro-Chain through Project Manager
  • Scored gold level certificate (highest) in NXP AI Connectivity Week
  • Participated in NXP India Mega-Tech Poster Event (In top 16)
Digital ElectronicsVery-Large-Scale Integration (VLSI)VerilogResearch and Development (R&D)Microsoft OfficeSoC+1

Education

Vellore Institute of Technology

Bachelor of Technology - B.Tech — Electronics and Communications Engineering

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