Saurabh Arora

Software Engineer

Delhi, India13 yrs experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in low power CPU subsystem design.
Proven track record in digital architecture development.
Extensive experience in FPGA-based designs.

Stackforce AI infers this person is a highly skilled engineer in semiconductor and digital design industries.

Contact

Skills

Other Skills

ASICApplication-Specific Integrated Circuits (ASIC)Design CompilerDigital ElectronicsDigital Signal ProcessingFPGAField-Programmable Gate Arrays (FPGA)Logic SynthesisMatlabNCSimRTL DesignSpyglassSynopsys PrimetimeTetramaxVHDL

About

Working as Staff Engineer with Qualcomm; responsible for the design and development of complex low power CPU Subsystems. Earlier worked on design of complex algorithmic digital architectures, that optimally meet high-speed/low-area needs of the Radar Subsystem. Previously, involved in design of high speed all-digital/mixed signal blocks for data/signal processing IPs. Experienced in FPGA based designs of high speed Network Switches.

Experience

Qualcomm

3 roles

Senior Staff Engineer

Promoted

Dec 2025 – Present · 3 mos

Staff Engineer

Dec 2022 – Nov 2025 · 2 yrs 11 mos

Senior Lead Engineer

Jan 2020 – Nov 2022 · 2 yrs 10 mos

Nxp semiconductors

Lead Design Engineer

Apr 2017 – Jan 2020 · 2 yrs 9 mos · Noida Area, India

Stmicroelectronics

3 roles

Technical Leader, TDP Division

Aug 2016 – Mar 2017 · 7 mos · Greater Noida

Worked on low-power Parallel-to-Serial Digital Interfaces.

Senior Design Engineer, TDP Division

Apr 2016 – Jul 2016 · 3 mos · Greater Noida

Worked on digital filter chains of signal processing IPs and Mixed Signal IPs.
► Developed the MATLAB model and RTL for Mixed Signal Thermal Sensors IP.
► Automated the filter chain of high precision sigma delta architecture ADC.
► Worked on low-power, high speed Parallel to Serial Digital Interface.

Senior Design Engineer, CPD Division

Sep 2014 – Mar 2016 · 1 yr 6 mos · Greater Noida

Worked on the microarchitecture development, RTL Design and entire RTL2GDS flow for Set Top Box digital IPs.
IP Ownerships:
► Secure Transport Front End(STFE) ⇛ Front End Set top Box IP.
► Transport Stream In Out(TSIO) ⇛ Security IP that streams packets to a Smart Card.
► TSIO PHY ⇛ Interface between TSIO and Smart Card
► Audio IP ⇛ Audio Data Processing
Responsibilities:
► Micro architecture Development
► RTL Design using Verilog, VHDL.
► Functional Simulations.
► CDC and Lint Checks using Spyglass.
► Synthesis
► Support to Verification teams.
Protocols:
► AXI
► STBus
Tools:
► Spyglass
► NCSim
► Design Compiler
► Tetramax
► Formality
► Conformal

Tejas networks

Research and Development Engineer, FPGA

Aug 2012 – Sep 2014 · 2 yrs 1 mo · Bengaluru Area, India

Worked on the Design and development of Network Switches.
► Worked on STM1 Circuit Emulation IP which allowed transmission of SDH circuits over a Packet Network.
► Worked on E1 Circuit Emulation which allowed emulation of TDM services over packet.
► Designed and developed the microarchitecture and RTL of RFC 2544 standard.
► Involved in development of Multiplexing V.35 data over E3 network.
► Designed Control FPGAs for various boards.
Responsibilities :
► Design Document and Programming Guide Development
► RTL Design using Verilog
► Running Functional Simulations.
► Static Timing Analysis
► FPGA On-board testing and debugging.
► Support To SW team.
Protocols :
► SPI
► I2C
► UART
► LPC
Tools:
► NCSIM
► Xilinx Coregen
► Lattice Diamond
Testers : Omniber, Calnex, EDT-135, Spirent, IXIA