Ankur Chaplot (Jain) — Software Engineer
JEE 172 BTech, Computer Science, IIT Delhi MTech, Computer Science, IIT Delhi Software Engineering Experiences: * Consummate C++/C++11 Architect, Programmer, Debugger and Tester. * Performance improvement of legacy tools. * Exhaustive Code Analysis, Peer Reviews and Refactoring. * Fixing the gotchas in Multi-processing techniques, RPC, IPC and Daemon processes. * Vast and pragmatic exposure to C++/OOP/STL/Boost. * Implemented variety of design patterns and carefully observed the nuances involved. * Expertise in shell scripting - perl/tk/ksh etc. * Debugging large software and multi-platform(OS) issue. * Application development in UNIX environment. Technical Skills * Worked on a variety of electronic design automation (EDA) products * Agile development of a large scale software product. + Algorithms for design rule violation detection in semiconductor manufacturing process. |_ Development of core infrastructure for design rule checking |_ Violation Fixing Techniques for 7nm and below + Improving performance of Virtuoso Schematic Editor. |_ BSTree/AVL |_ Geometrical Concepts - Scans, Corner Stitching, Routing + Concepts and Techniques in Mixed Signal Front-end software. |_ Design translators (Import) |_ VHDL, VERILOG, SPICE, SPECTRE, CDL |_ Netlisters (Export): |_VHDL, VERILOG + Text Support in Virtuoso (Text_In_DFII) |_ A Step toward seamless IP integration. Specialties: C++11/C++/STL/OOP/Algorithms/Data Structures Strongly motivated towards learning new technology and putting them into application development. Expert in customer interaction for product proliferation.
Stackforce AI infers this person is a highly skilled Software Architect in the EDA industry with a focus on performance optimization.
Location: South Delhi, Delhi, India
Experience: 23 yrs 5 mos
Skills
- C++
- Routing Algorithms
- Computational Geometric Algorithms
- C/c++
- Mixed Signal Design Technologies
- Testing
- Validation
Career Highlights
- Expert in C++ with extensive experience in EDA products.
- Proven track record in performance optimization and routing algorithms.
- Strong leadership in large-scale software development projects.
Work Experience
Cadence Design Systems
Software Architect (5 yrs 8 mos)
Senior Principal Software Engineer (5 yrs 11 mos)
Member of Consulting Staff (3 yrs 11 mos)
Senior Member Of Technical Staff (4 yrs 5 mos)
Intel
Senior Component Design Engineer (11 mos)
Component Design Engineer (2 yrs 6 mos)
Education
BTech+MTech at Indian Institute of Technology, Delhi
at vidya niketan, bhilwara