Ankur Chaplot (Jain)

Software Engineer

South Delhi, Delhi, India23 yrs 5 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in C++ with extensive experience in EDA products.
  • Proven track record in performance optimization and routing algorithms.
  • Strong leadership in large-scale software development projects.
Stackforce AI infers this person is a highly skilled Software Architect in the EDA industry with a focus on performance optimization.

Contact

Skills

Core Skills

C++Routing AlgorithmsComputational Geometric AlgorithmsC/c++Mixed Signal Design TechnologiesTestingValidation

Other Skills

AlgorithmsCC/C++ STLData StructuresDebuggingDesign PatternsDjangoEDAEclipseGraph SearchGraph Search TechniquesLithography Aware Design Rule CheckingOOPObject Oriented DesignOptimization Techniques

About

JEE 172 BTech, Computer Science, IIT Delhi MTech, Computer Science, IIT Delhi Software Engineering Experiences: * Consummate C++/C++11 Architect, Programmer, Debugger and Tester. * Performance improvement of legacy tools. * Exhaustive Code Analysis, Peer Reviews and Refactoring. * Fixing the gotchas in Multi-processing techniques, RPC, IPC and Daemon processes. * Vast and pragmatic exposure to C++/OOP/STL/Boost. * Implemented variety of design patterns and carefully observed the nuances involved. * Expertise in shell scripting - perl/tk/ksh etc. * Debugging large software and multi-platform(OS) issue. * Application development in UNIX environment. Technical Skills * Worked on a variety of electronic design automation (EDA) products * Agile development of a large scale software product. + Algorithms for design rule violation detection in semiconductor manufacturing process. |_ Development of core infrastructure for design rule checking |_ Violation Fixing Techniques for 7nm and below + Improving performance of Virtuoso Schematic Editor. |_ BSTree/AVL |_ Geometrical Concepts - Scans, Corner Stitching, Routing + Concepts and Techniques in Mixed Signal Front-end software. |_ Design translators (Import) |_ VHDL, VERILOG, SPICE, SPECTRE, CDL |_ Netlisters (Export): |_VHDL, VERILOG + Text Support in Virtuoso (Text_In_DFII) |_ A Step toward seamless IP integration. Specialties: C++11/C++/STL/OOP/Algorithms/Data Structures Strongly motivated towards learning new technology and putting them into application development. Expert in customer interaction for product proliferation.

Experience

Cadence design systems

4 roles

Software Architect

Promoted

Jul 2020Present · 5 yrs 8 mos

  • Managing product and team of inhouse developed large scale VLSI Custom Digital Router. Expert in graph search techniques and pragmatic experience with Routing Algorithms - A*Search and other ancillaries.
  • Focusing on scaling for performance and data size and improvising on quality of routing.
C++Graph Search TechniquesRouting Algorithms

Senior Principal Software Engineer

Jul 2014Jun 2020 · 5 yrs 11 mos

  • Project Leadership and code assessment
  • C++ Large scale software development
  • Lithography aware design rule checkin engine
  • Computational Geometric Algorithms
  • Graph search
  • optimization techniques
C++Lithography Aware Design Rule CheckingComputational Geometric AlgorithmsGraph SearchOptimization Techniques

Member of Consulting Staff

Promoted

Jul 2010Jun 2014 · 3 yrs 11 mos

  • Netlister and Design Translators
  • C/C++, SKILL, UNIX scripting
  • Mixed Signal Design Technologies
  • Custom IC Front End Softwares
C/C++SKILLUNIX ScriptingMixed Signal Design Technologies

Senior Member Of Technical Staff

Jan 2006Jun 2010 · 4 yrs 5 mos

Intel

2 roles

Senior Component Design Engineer

Promoted

Jan 2005Dec 2005 · 11 mos

  • Worked as Design automation engineer. Expertise in Testing and Validation.
  • Prowess in Perl/C
TestingValidationPerlC

Component Design Engineer

Jul 2002Jan 2005 · 2 yrs 6 mos

Education

Indian Institute of Technology, Delhi

BTech+MTech — Computer Science and Engineering

Jan 1997Jan 2002

vidya niketan, bhilwara

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