Abhinav Rathore

Software Engineer

Bengaluru, Karnataka, India15 yrs 11 mos experience
Highly Stable

Key Highlights

  • 15+ years in ASIC and FPGA domains.
  • Expert in PCIe technologies and SmartNIC architectures.
  • Leading development of AI connectivity solutions.
Stackforce AI infers this person is a highly skilled engineer in the semiconductor and telecommunications industries.

Contact

Skills

Core Skills

PcieDmaHigh-frequency TradingSystemverilogFpgaAsicVlsiDigital Design

Other Skills

AllegroCCadence Schematic CaptureCharacterizationDDR3EthernetField-Programmable Gate Arrays (FPGA)HFTIntegrated Circuit DesignInternet Protocol Suite (TCP/IP)LVDSLabVIEWLogic DesignOrCADPCIe PIPE

About

Highly experienced digital design and hardware systems engineer with 15+ years of industry expertise spanning ASIC and FPGA domains, PCIe Gen4/5/6/7 technologies, DMA engines, SmartNIC architectures, and ultra-low latency systems for financial and cloud infrastructure. Currently focused on the development of next-generation AI connectivity solutions that enable scalable, high-performance interconnects for both scale-up and scale-out architectures in hyperscale data centers. Emphasis is on designing AI-optimized fabrics and protocols to support massive data movement essential for advanced AI workloads. Previously led high-impact programs at Intel, overseeing architecture, RTL design, and validation of PCIe/DMA IPs and SmartNIC platforms, driving innovation and successful delivery of complex hardware systems.

Experience

Astera labs

Principal Engineer

Mar 2025Present · 1 yr

Intel corporation

2 roles

Techinical Lead IP Design

Feb 2022Mar 2025 · 3 yrs 1 mo · Bengaluru Area, India

IP Logic Design Engineer

Jul 2019Feb 2022 · 2 yrs 7 mos · Bengaluru Area, India

  • Leading Development of PCIe Subsystem & PIPE | Next-Gen DMA IPs for Intel PCIe Gen4/5 FPGAs in Cloud & Accelerated Applications
DMAPCIePCIe PIPE

Apt portfolio private limited

Low Latency HFT Platform Development

Aug 2017Jul 2019 · 1 yr 11 mos · Bangalore

  • Orderbook design for both MBP/MBO (NSE). Execution Report parser and UDP broadcaster for CME.
  • Module level verification using python based models.
  • Deployed inhouse validation rig that could play offline market data to passively test the FPGA solution.
Python (Programming Language)SystemVerilogInternet Protocol Suite (TCP/IP)User Datagram Protocol (UDP)EthernetHigh-Frequency Trading

Qualcomm

FPGA Design Specialist

Aug 2015Jul 2017 · 1 yr 11 mos · Bangalore

  • FPGA platform development for Qualcomm Wireless and RF products R&D
  • Developed novel FPGA based HTOL system cascading multiple FPGA devices communicating over high speed parallel (FMC based) interface or Ethernet that considerably increased the capacity to parallelly test multiple RF Modems gaining significant test time reduction.
  • Handled end-to-end solution including IP/ RTL Design, Verilog based testbenches, schematic reviews, component selection, LabVIEW integration and finally bring up and deployment.
LabVIEWAllegroRFFEFPGA

Lattice semiconductor

System Design Engineer

Jan 2011Aug 2015 · 4 yrs 7 mos · Bangalore

  • Developing consumer mobile system designs/proof of concept for top handset OEMs like Infrared xcvrs, barcode scanners, always on displays with tap to wake and pedometer etc..
  • Building reference designs for Lattice FPGAs ECP3 etc. and supporting field/sales and customers with their designs across all Lattice Products.
  • 1st to market with USB Type C PD solution including IP/RTL Design, analog front-end design, prototyping and finally demoing the solution at USB interop
CharacterizationSerDesLVDSCadence Schematic CaptureDDR3PCIe+2

Delopt

Design Engineer

Mar 2010Dec 2010 · 9 mos

  • Digital Design/Simulation on Xilinx FPGAs (Virtex series) in VHDL and Verilog.
  • Schematic entry and component creation using Orcad.
VerilogVHDLOrCADDigital Design

Education

Centre for Development of Advanced Computing (C-DAC)

Postgraduate Degree — VLSI

Aug 2009Feb 2010

Dr. A.P.J. Abdul Kalam Technical University

Bachelor of Technology - BTech

Aug 2005Jun 2009

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