Akash Tomar

Software Engineer

Delhi, India9 yrs 6 mos experience

Highly StableAI Enabled

Key Highlights

Expert in PCIe and verification methodologies.
Strong background in digital circuit design.
Proven experience in semiconductor industry projects.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in PCIe technologies.

Contact

Skills

Core Skills

PcieVerification And Validation

Other Skills

AXI interfaceAdvanced computingApp BFM for PCIe gen6Artificial Intelligence (AI)Bus functional modelCC++Computer ArchitectureDMADPUData center NICDebugging PCIe failuresDigital Circuit DesignEDAError injection

About

Currently working as Design Engineer -2 at AMD. Prior joining to AMD, I worked with Synopsys for 3 years. Strong professional background in PCIe, Axi, UVM, Verilog, System verilog and sound knowledge of OOPS, C++ and data structures-algorithms. Good experience in front-end digital Verilog projects. Sound knowledge of HW-SW co-design with use of xilinx zynq 7000 Soc. Completed my Bachelor's in Technology in Electrical Engineering in June 2020. Always keen to learn and gain more knowledge and experience.

Experience

Amd

2 roles

Senior Silicon Design Engineer

Promoted

Nov 2025 – Present · 4 mos · Hyderabad, Telangana, India

Silicon Design Engineer 2

Jul 2023 – Nov 2025 · 2 yrs 4 mos · Hyderabad, Telangana, India

Synopsys inc

2 roles

Research And Development Engineer -2

Feb 2023 – Jul 2023 · 5 mos · Delhi, India · On-site

Responsible for PCIe gen6 VIP developement and verification. Exposure to PCIe customers engagement to handle important deliverable. Responsible for debugging PCIe failures and maintain stability in gen5/gen6. Development of Scoreboard, App bfm for PCIe gen6.

PCIe gen6 VIP developmentVerification and ValidationDebugging PCIe failuresScoreboard developmentApp BFM for PCIe gen6PCIe

R&D Engineer -1

Jul 2020 – Jan 2023 · 2 yrs 6 mos · Delhi, India · On-site

Working on PCIe gen6 features verification and validation with AXI interface using in-house Synopsys PCIe-AXI Controller IP. Responsible for adding negative error injection, corner scenarios for PCIe features. Exposure to protocol check coverage,functional coverage closure for PCIe gen 5/ gen6. Experience in collaborating with PL/PHY teams for complete PCIe gen 6 verification bring up and experience in working with PCIe teams globally .

PCIe gen6 features verificationAXI interfaceError injectionProtocol check coverageFunctional coverage closurePCIe+1