Piyush Jain

Software Engineer

Bengaluru, Karnataka, India13 yrs 10 mos experience

Key Highlights

  • Expert in ASIC design and RTL methodologies.
  • Proficient in Verilog and System Verilog for VLSI projects.
  • Strong background in SoC and RTL debugging.
Stackforce AI infers this person is a VLSI ASIC Design Engineer with expertise in RTL methodologies.

Contact

Skills

Core Skills

AsicRtl Design

Other Skills

RTL debuggingSoCSystem VerilogVLSIVerilog

Experience

13 yrs 10 mos
Total Experience
13 yrs 10 mos
Average Tenure
13 yrs 10 mos
Current Experience

Juniper networks

ASIC Design Engineer

Jul 2012Present · 13 yrs 10 mos · Bengaluru , India

VerilogSystem VerilogVLSISoCASICRTL design+1

Education

Birla Institute of Technology and Science, Pilani

Bachelor of Engineering (B.E.) — Electrical and Electronics Engineering

Jan 2008Jan 2012

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