Mar 2020 – Present · 6 yrs 1 mo

• Leading a team of Engineers working on Functional Verification of Tx part for 5G subsystems, Common Bus IP Verification as well as MIPS Verification.
• MIPS Verification involves multiple environments using SV/UVM/C having assembly test cases as well as instruction accurate simulator models, traces etc
• Tx verification of 5G subsystem randomized DPI based UVM environment built from scratch by team. This environment has been used to verify multiple 5G sub6G and mmwave chips as well as ensuring smooth SW and chip bring-ups
• Common Bus IP verification involves from scratch building of UVM environments for multiple IP's used across SOC's ranging from bus bridges as well as performance enhancing IP's. These IP's are mainly focused on ARM buses or internal bus protocols

Feb 2015 – Feb 2020 · 5 yrs

• Worked on 5G Subsystem Verification as well as Bus Matrix Verification for Modem Subsystems