Jan 2025 – Present · 1 yr 2 mos · Bangalore Urban, Karnataka, India · Hybrid

• EXECOM member of IEEE Bangalore Section from January 2025.

Nov 2024 – Present · 1 yr 4 mos · Bangalore Urban, Karnataka, India

Sep 2021 – Nov 2024 · 3 yrs 2 mos · Bangalore Urban, Karnataka, India

• I am the global Formal Verification Lead and Manager in GCAD team, Qualcomm, leading formal verification charter, on the fronts of methodology/tool-flow development and deployment globally. My role involves defining the strategy and roadmap for formal verification in Qualcomm across all BUs, managing and collaborating with EDA vendors for improving the formal tools and flows. I have been instrumental in building the GCAD formal verification team from scratch and currently managing 8 engineers. I am also managing 50+ consultants from multiple EDA vendors, primarily Synopsys and Cadence.
• Additionally, I serve as QWomen BDC Board member in Qualcomm, driving inclusion and diversity activities and working on mentoring and organizing multiple events targeted to long term career growth of our women engineers. I serve on the technical program committee as track chair for prestigious internal conference in Qualcomm.

Oct 2019 – Sep 2021 · 1 yr 11 mos

• I managed the Zebu Debug R&D team in India, which is part of a global cross-geography R&D team responsible for development of the debug tool-suite of ZeBu, which is Synopsys’ leading emulation system. Our primary responsibility has been designing /architecting /implementing /maintaining software for enhancing the existing flow of ZeBu Debug.
• I have also been involved in inclusion and diversity activities at Synopsys and have mentored women engineers in their career path.

Jul 2018 – Oct 2019 · 1 yr 3 mos

• Worked on enhancement / designing new features and supporting existing features /fixing issues in Zebu post-run debug tool-suite, which helps to rerun deterministically critical error-prone part of emulation in Zebu. I owned the state comparison tool-suite in post-run debug.

Jun 2016 – Jun 2018 · 2 yrs

• I was a key member of the low power static verification VC-LP R&D team. Also worked on architecting and developing from scratch some generic platform features of the static verification tool VC-STATIC.

Feb 2015 – May 2016 · 1 yr 3 mos

• I worked in the low power static verification VC-LP R&D team for developing new features from scratch and supporting existing features of the tool.

Jun 2012 – Feb 2015 · 2 yrs 8 mos · Bengaluru Area, India

• Lead the Formal Verification (FV) India team for System Z, IBM's mainframe processor. Responsibilities include developing methodology for extensive deployment of FV, development of formal verification environment for designs using SixthSense from scratch, understanding design architecture/ correctness requirements by designer interactions. Mentoring verification engineers applying FV technologies on system Z, ramped up around 10 people having no FV background.
• Deployed FV methodology on multiple core and pervasive units / blocks of Z for the first time. The main focus is to guarantee design correctness and catch corner case bugs as early as possible in the design cycle. Written 12000+ lines of VHDL code for drivers and reference models by understanding architectural details for:
• Transition correctness and specifically absence of hangs in control state machines of various core units e.g. fixed and floating point units, recovery unit, coprocessor for encryption/decryption etc.
• Execution units for arithmetic instructions, eg. multiplies, divides etc.
• Correctness and specifically absence of hangs of control logic in the load-store unit.
• Branch prediction algorithms verification in the instruction fetch unit.
• Formal techniques of Sequential Equivalence Checking (SEC) between two versions of a design.
• Correctness of LRU logic, set delete logic for arrays, arbitration logic, power management unit components.
• Innovated and drove a novel methodology for application of formal methods in fault tolerance verification/soft error detection analysis methodology for hardware designs.
• Formulation of suitable abstractions (over-approximations, under-approximations), decompositions and various such strategies in order to scale FV technology according to the requirements of complex logic.
• Published and presented 4 papers in IBM internal global conferences, guided the thesis of an M. Tech intern.

Feb 2010 – Sep 2010 · 7 mos · Bengaluru Area, India

• Objective was to deploy the prototype tool, Bug Fix Verifier (BFV), that I had developed leveraging formal methods for bug fix classification of hardware designs as part of my PhD research on actual Intel RTL.

Mar 2007 – May 2012 · 5 yrs 2 mos · Kharagpur Area, India

• Worked as Research Consultant at Sponsored Research and Industrial Consultancy (SRIC), IIT Kharagpur in industry-academia collaborative research projects, during my PhD tenure at IIT Kharagpur.
• Worked in the following research projects and developed and demonstrated prototype tools, published several conference and journal papers related to them.
• Formal Verification of Post Silicon Bug Fixes (Intel Technology India Pvt. Ltd., Bangalore)
• Leveraging Simulation History for FPV (Intel Technology India Pvt. Ltd., Bangalore)
• Coverage Metrics for Design Intent Coverage (Intel Corporation, USA)
• Formal Methods for Power Intent Verification in Multi-Voltage Designs (Synopsys
• Inc., Bangalore)

Jun 2006 – Mar 2007 · 9 mos · Kolkata Area, India

• Worked as development engineer in the Video Team of the network testing product
• IxLoad, involving layers 4 to 7 in networking domain.