Jyoti Tapariya

Software Engineer

Cambridge, England, United Kingdom8 yrs 9 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Architectural and RTL formal sign-off.
Proficient in leading formal verification tools.
Strong background in hardware verification methodologies.

Stackforce AI infers this person is a Formal Verification Engineer with expertise in hardware verification and architectural design.

Contact

Skills

Other Skills

Assertion Based VerificationFormal VerificationGitHardware VerificationJasperGoldMicrosoft OfficeScriptingSystemVerilogTest PlanningUniversal Verification Methodology (UVM)VC Formal

About

Experienced in Architectural and RTL formal sign-off using leading formal verification tools.

Experience

Qualcomm

2 roles

Senior Staff Engineer

Promoted

Jul 2024 – Present · 1 yr 8 mos

Staff Engineer

Oct 2022 – Jun 2024 · 1 yr 8 mos

Intel corporation

Validation Engineer

May 2020 – Oct 2022 · 2 yrs 5 mos · Bengaluru, Karnataka, India

Oski technology

Formal Verification Engineer

Jun 2017 – May 2020 · 2 yrs 11 mos · Gurugram, Haryana, India

Indian institute of technology, guwahati

Summer Internship

May 2016 – Jul 2016 · 2 mos · Guwahati, Assam, India

Education

Maulana Azad National Institute of Technology

Bachelor of Technology — Electronics and Communications Engineering

Jan 2013 – Jan 2017

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