Feb 2016 – Mar 2017 · 1 yr 1 mo

• Ajay Manages a vital function of the Product Deployment role to facilitate the proliferation and deployment of C-to-RTL-to-GDSII products,
• flows and methodologies. Responsible for managing the worldwide campaign of C-to-GDSII products and supervises multiple resources
• to meet the division’s business goals. This is a growing IC design complexities that cause most IC Architect to look for smart and efficient
• electronic design automation solutions to improve IC performance and time to market while avoiding technological barriers in between
• domain boundaries

Jan 2012 – Feb 2016 · 4 yrs 1 mo

• Built a high-performing Product Engineering team from the ground up using local talent, focused on RTL-to-GDSII methodology—including Optimization, Floorplanning, Clock Tree Synthesis (CTS), and Logic-Level Floorplanning engines.
• Managed multiple customer engagements and led teams to drive RTL2GDS flows within IC Implementation product lines.
• Specialized in Logical/Physical RTL Synthesis, RTL Floorplanning, and P&R solutions, enhancing design efficiency.
• Collaborated with diverse customers across various design styles and application domains, adapting to different complexities and process geometries.

Jun 2007 – Jan 2012 · 4 yrs 7 mos

Feb 2007 – Jun 2007 · 4 mos · Noida Area, India

Jan 2006 – Jan 2007 · 1 yr

• Worked on a full chip (90nm) where was responsible for following responsibilities. Top Level : Partitioning, Floor plan, Power grid planning CTS, Timing Physical Verification, Chip Finishing. All the Back End Deliveries to the customers. Working on ARM926(65nm) Hardening, as a Back-End Lead and responsible for Floor plan, CTS and whole netlist to GDSII flow and after that back end support for different Projects and documentation.

Jan 2001 – Jan 2007 · 6 yrs

• Worked in DSG (Design Solution Group), is the Physical Design's SoC design services organization providing Philips product development teams with best in class SoC design services from specification to prototype approval. In which, working as a Physical Design Engineer having responsibilities for RTL2GDS2 design and flow.

Sep 2000 – Mar 2001 · 6 mos · Folsom CA, USA

• Worked as Static Timing Analysis engineer for chiplets for the high speed processors

Jan 1998 – Jan 2000 · 2 yrs · Noida Area, India

• Ajay was involved in x86 processor design, system-on-chip design, writing device drivers for the Windows 95 / NT and FPGA design. Ajay was working as a physical Design Engineer having following responsibilities.
• Floor planning and integration of small chiplets
• Place and Route
• Physical Verification
• ECO and timing closure;
• GDSII database release;