Sep 2011 – Apr 2019 · 7 yrs 7 mos

• Hardware emulation is a verification methodology that SoC designers use to debug their designs.
• It allows for the most accurate representation of the SoC before the actual hardware is available.
• I was driving the validation of a diverse range of emulation applications such as fault injection, DFT pattern acceleration, average / peak power estimation, functional coverage, software debug on the emulator and advanced trigger techniques.
• My other tasks involved the validation of features in the Veloce OS3 suite of products.
• Deeply involved with :
• Review of functional and design specifications.
• Proposing test plans for new test bench acceleration methodologies.
• Enhancing test coverage.
• Executing test plan .
• Creating use model cases similar to the end user flow.
• Quality analysis of the product.
• Defects analysis and proposing focus areas for the development team/ product team.
• Leading, training, mentoring a team of 6-8 engineers.
• Functional and Line coverage,
• Power analysis,
• SVA,
• Release Quality Control,
• Regression planning and management.
• Hands on with C/C++, Verilog, System Verilog, VHDL, ease of use analysis, customer centered testing and quality assurance for complex EDA products , developing high performance teams.

Jul 2000 – Aug 2011 · 11 yrs 1 mo

• Veloce runtime C/C++ APIs design and development.
• Veloce runtime integration with GUI.
• Veloce runtime integration with TBX.
• Scaling the runtime system to support > 100M sized designs.
• Trigger feature related software development for the various veloce platforms from the scratch.
• Line Breakproint system for veloce.
• Mixed VHDL/Verilog visibility support.
• Prototype development for power analysis on veloce.
• Prototype development for design coverage and UCDB generation from veloce waveform db.
• Veloce trigger system :
• Design and development of trigger and logic analyzer system for the emulator. Software development, test plan, hardware-software integration for trigger system and line breakpoint system.
• Bug tracking and follow up with the major stake holders.
• Leading and mentoring a team of 3-4 engineers.
• Improving the software engineering / QA processes followed by the software development team.
• RTL to waveform visibility tools .
• Frontend support for mixed VHDL/verilog on the emulator.
• Mixed vhdl/verilog to FSDB generator.
• Mixed vhdl/verilog debug on Virtualogic emulator (VStation).
• Trigger for mixed vhdl/verilog designs.
• Backend compiler support for simulation acceleration platform (IKOS NSIM/Voyager).
• NDL to vhdl generator.
• Binary stimulus to VCD tool.
• C/C++ developer, product development manager, quality assurance expert .

Aug 1998 – Jul 2000 · 1 yr 11 mos · Hyderabad

• Enterprise solutions.
• C++, Java, VC++.