Aug 2018 – Jun 2019 · 10 mos

• My latest work revolves around adding support of VHDL2008 in Compiler, finding solutions in object oriented space and application of design patterns. I have supported various language features for RTL Compiler.
• Working in Mentor Graphics has provided me with an opportunity to work with smart people in a very team oriented environment which brings out the best in me.

Aug 2015 – Jul 2018 · 2 yrs 11 mos

Aug 2013 – Jul 2015 · 1 yr 11 mos

• Worked in development of C/C++ based core compiler/synthesis engine. The compiler converts high level HDL(verilog/vhdl) into optimized gates(OR/AND/NOT gates) . Developed various robust data structures and algorithms used in the flow. The work involves problem analysis, designing solution, implementation, verification and customer support.
• First Prize in Mentor Code Contest - 2011.
• Added support for VHDL 2008 in RTL compiler using C++ language.
• Memory and run time optimization of RTL Compiler.

Jun 2011 – Jul 2013 · 2 yrs 1 mo

• Developed support for new constructs in System Verilog using C++ language.
• Added support of hier-ref.

May 2010 – Jun 2010 · 1 mo · Noida

• Developed synthesizable models of Synopsys Design Ware components.
• Performance improvements in time to compile and compiler memory footprint.