Soumya Palit

Software Engineer

Noida, Uttar Pradesh, India16 yrs 5 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in C/C++ and System Verilog.
Proven track record in software engineering and design.
Strong background in algorithms and data structures.

Stackforce AI infers this person is a seasoned software engineer specializing in EDA and system design.

Contact

Skills

Other Skills

PerlCore JavaSystem VeriloggdbGNU DebuggerVHDLDDDVimJavaTCLCVSEDAScriptingMultithreadingDebugging

About

Coding : C, C++, Verilog Scripting : AWK, Shell Script (Unix) Platform : Windows, Linux/Unix, Solaris Concepts : Data Structure, Operating System Concepts, Aglorithms

Experience

Cadence design systems

2 roles

Sr. Principal Software Engineer

Promoted

Jul 2022 – Present · 3 yrs 8 mos

Principal Software Engineer

Aug 2020 – Jul 2022 · 1 yr 11 mos

Mentor graphics

2 roles

Member Of Consulting Staff

Jul 2017 – Aug 2020 · 3 yrs 1 mo · Noida Area, India

LMTS

Jul 2015 – Jul 2017 · 2 yrs · Noida Area, India

Sequence design

R & D Engineer

Jul 2012 – Jul 2015 · 3 yrs · Noida Area, India

Working on Apache's Static Timing Analysis tool and Clock Jitter Solution tool

Atrenta | interra systems

Engineer | Individual Contractor

Jul 2011 – Sep 2011 · 2 mos · Noida Area, India

Enhancement: IP-Xact support for Banks for their tool Gensys.
Added support for various tcl commands in their tool for the same.
Added PTT support for generation of Verilog and VHDL files that are generated by Gensys

Interra systems

Senior Engineer

Dec 2010 – Jul 2012 · 1 yr 7 mos · Kolkata Area, India

Working on the Cheetah system verilog analyser parser.
Various bug-fixes, optimization, implementation of the enhancement incorporated in System Verilog.
Worked on generic and static iterator used to browse the Cheetah-Object model.