Jul 2019 – Aug 2022 · 3 yrs 1 mo · Mountain View, California, United States

• Worked on uArch and design of IPs in XBOX and ML Accelerator chips
• Developed micro-architecture and wrote custom RTL for Color Processing IP within Image/Video Encoder of XBOX
• Designed Input/Output buffer management units interfacing with DMA through AXI protocol and storing RGB pixels
• Implemented heavily pipelined arithmetic blocks like Normalization, Color Space Conversion, and Gamma Correction
• Designed global interconnect network fabrics (data/message/config) for ML accelerator with deadlock avoidance
• Developed custom SV based RTL for ECC/parity encoder/decoder, Address Translator, and Network A/B Selector

Aug 2018 – Dec 2018 · 4 mos · Portland, Oregon Metropolitan Area

• Worked on early RTL power estimation and analysis-driven power reduction to optimize designs using Power Artist
• Integrated modules into a sub-system, and generated Spyglass CDC abstract for timing/synchronization constraints

May 2018 – Aug 2018 · 3 mos · Cupertino, California

• Implemented a complete view generation lifecycle by creating Makefiles for conversion from GDS to Oasis view
• Created an EDA tool-based QA Test using Makefile/Perl, and optimized it for efficient run time and resource usage

Mar 2018 – Mar 2018 · 0 mo · San Jose, California

• I worked as a Teaching Assistant for the Deep Learning Instructor-led Workshops during Nvidia GPU Technology Conference held from March 25-29, 2018.

Jul 2015 – Jun 2017 · 1 yr 11 mos

• Performed functional verification and testcase development of tributary interface modules using SV in an UVM env
• Developed verification strategy and testplan for GCC IP using SystemVerilog based Constrained Random Verification
• Created a library of SystemVerilog Assertion (SVA) based checkers for asynchronous and synchronous FIFOs
• Performed Formal Property Verification (FPV) on various functional blocks using Cadence Jasper Gold and Synopsys Verdi

Jan 2015 – Jun 2015 · 5 mos

• Prepared verification strategies including test plans and coverage requirements for FIFO based memory sub-system.
• Implemented SVA based checkers/scoreboards which have been approved to bind with various functional blocks used in the company’s ongoing project on chip design for high speed optical networks.
• Prepared assertion based Interface for peripheral interconnects using System Verilog and UVM.

May 2014 – Jul 2014 · 2 mos · Hsinchu City, Taiwan, Taiwan

• My responsibilities included implementation of a file system for volumes formatted FAT32 using Code Composer Studio IDE for TI control card. I succeeded in providing an innovative design of a FAT driver for reading/writing 16-bit Micro SD card with 32-bit TMS320F28035 TI control card which was approved for using in the company’s ongoing project on vibration meter device.

May 2013 – Jul 2013 · 2 mos · Pilani, Rajasthan, India

• I worked on ‘Navigation Scheme for Autonomous Underwater Vehicle (AUV)’, a project funded by the Govt. of India. My responsibilities included development of an inertial navigation system using accelerometer, depth sensors, altimeter, UV range finder and GPS system by interfacing with FriendlyARM Mini 2440 (ARM9 series).

May 2012 – Jul 2012 · 2 mos · Greater Delhi Area

• I worked as an analyst for the skill-mapping of the recruiting firms in IGI airport industry and assisted DIAL (Delhi International Airport Limited) in its real-time project to design templates for survey questionnaires using MS Excel for a direct market survey on the job-recruitment system of various firms. For my work, I have been personally recommended by Ms. Meena Raghunathan, Director of GMRVF.