Nishant Nerpagar

Director of Engineering

Pune, Maharashtra, India20 yrs 5 mos experience
Highly Stable

Key Highlights

  • Expert in FPGA design and validation.
  • Strong leadership in managing technical teams.
  • Proficient in multiple programming languages for FPGA.
Stackforce AI infers this person is a specialist in FPGA design and validation within the electronics industry.

Contact

Skills

Core Skills

FpgaVhdlUsb Type-c Pd Ip

Other Skills

AXI communication protocolApplication-Specific Integrated Circuits (ASIC)DDR2DDR3Electronics Hardware DesignEmbedded C/C++Embedded SystemsFPGA development tool Xilinx VivadoFPGA prototypingField-Programmable Gate Arrays (FPGA)MatlabPCB DesignQuestaSimSemiconductorsSoC

About

Manager Key Role Performed:  Experience with USB TYPE- C PD IP designing & validation on FPGA  Experience with leading the Team.  Product Planning, Requirement Analysis, Architecture Design, Resource Management,  Team Handling, Client Interaction, Production Plan, Design Review, Timeline & Project Delivery.  Prepared Scope, Proposals and Estimation for new project opportunities.  Expertise in VHDL and Verilog & System Verilog languages for Module/IP design for FPGAs  Worked on Prototyping of signal and image/video processing algorithms on FPGAs based on system requirements  Experience in Embedded C/C++ programming for processing systems on Zynq SOCs  Experience in AXI communication protocol(AXI4, AXI-lite, AXI-Stream) for interfacing FPGA blocks  Experience in interfacing FPGA with peripheral devices such as ADCs, DACs, DDR, microcontrollers, serializers, deserializer  Worked on implementation of a communication protocol such as UART, SPI, I2C for peripheral devices interface  Experience in working on STA and CDC techniques  Expertise in using FPGA development tool Xilinx Vivado/SDK and simulation tool QusetaSim  Experience in creating simulation environment for IP/Module verification and defining test cases for regression testing using python scripting With VUNIT  Have good debugging skills for FPGA design using Tcl scripting as well as system-level debugging using logic analyzers and oscilloscope  Board Bring-up, Debugging.  Experience in creating detail documentation for FPGA design  FPGA USED: Spartan7, Artix7, Spartan6, Spartan3A, Spartan3AN, Spartan3E, Lattice ice40  SOC USED: Agilex-I series SOC ,Zynq-7000, Zynq ultrascale+ MPSoc, ZYNQ RF Soc  Experience with AD9361 RFADC  Experience with AFE2256 for XRAY machine  Experience with : CYUSB3014 (USB3.0),FT600Q(USB3.0) FT2232 USB fifo  Experience with Schematic Design in Cadstar, ORCAD & Altium, Layout Design in Altium & BOM Part Selections.  Worked on implementation of a communication protocol such as USB TYPE- C PD, QC, AXI, DDR3, DDR2, NAND/NOR Flash, Ethernet GMII/MII, RS232, RS485, SPI, I2C, LCD, HDMI, GSM, GPS, Wi-Fi, Xbee, I2S, Bluetooth  High speed interface: DDR3, DDR2, USB3.0, USB2.0, Serializer /Deserializer, ADC, DAC, XADC, LVDS  IDE’s/ Tools: Xilinx ISE-14.7, Phan Ahead, Vivado19.1, EDK, Lattice tool, Quartus Prime 23.1  Verification Tools Questa sim19.1, Model Sim 6.3, Chip Scope  Document version control: PTC Integrity, GitHub  experience with S- curve design for BLDC Motor, servo motor  interface rotary & linear encoders with fpga

Experience

Quasar software defined radio

Team Lead Manager (FPGA Design)

Sep 2023Present · 2 yrs 6 mos · Pune, Maharashtra, India · On-site

FPGAUSB TYPE-C PD IPVHDLVerilogSystem VerilogEmbedded C/C+++3

Saankhya labs pvt ltd

Manager IC Design

Aug 2022Jan 2024 · 1 yr 5 mos · Pune, Maharashtra, India

FPGAVHDLVerilogSystem VerilogEmbedded C/C++AXI communication protocol+2

Magna electronics

Sr. FPGA Design Engineer

May 2018Aug 2022 · 4 yrs 3 mos · Pune/Pimpri-Chinchwad Area

FPGAVHDLVerilogSystem VerilogEmbedded C/C++AXI communication protocol+2

Siliconch systems

Sr. FPGA Design Engineer

Feb 2017May 2018 · 1 yr 3 mos · Bengaluru

  • working on USB Type-C IP validation
USB TYPE-C PD IPFPGAVHDLVerilogSystem Verilog

Macart equipments pvt. ltd. - india

Sr.FPGA Design Engineer

Jun 2010Feb 2017 · 6 yrs 8 mos · Pune/Pimpri-Chinchwad Area

Bit advance

FPGA Design Engineer

Feb 2007Jun 2010 · 3 yrs 4 mos

Jayashree electron (p) ltd

1

Jun 2005Sep 2006 · 1 yr 3 mos

Education

North Maharashtra University

M.Sc — Electronics

Jan 2003Jan 2005

S.S.V.P.S Dhule

BSc — Electronics

Jan 2000Jan 2003

ICIT (P) LTD, Pune University

PG diploma — VLSI Design

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