Jyothish Prakash — Software Engineer
Experienced IP Logic Design Engineer with a demonstrated history of working in VLSI industry. Skilled in SystemVerilog, verilog, Low power Design. Strong engineering professional with a Master of Technology (M.Tech.) focused in Embedded Systems from National institute of electronics and information technology(NIELIT).
Stackforce AI infers this person is a VLSI and FPGA design expert in the semiconductor industry.
Location: Bengaluru, Karnataka, India
Experience: 14 yrs 6 mos
Career Highlights
- Expertise in Low-power Design and VLSI.
- Strong background in SystemVerilog and RTL Development.
- Proven experience in High Frequency Trading FPGA development.
Work Experience
Intel Corporation
IP Logic Design Engineer (3 yrs 11 mos)
Megh Computing, Inc.
Senior RTL design engineer (3 yrs 3 mos)
APT Portfolio
High Frequency Trading (HFT) FPGA RTL Developer (1 yr 6 mos)
QuEST Global
Senior RTL Design Engineer (1 yr 8 mos)
Mistral Solutions Pvt. Ltd
Senior RTL design engineer (4 yrs 2 mos)
Education
Master of Technology (M.Tech.) at National institute of electronics and information technology(NIELIT)
Bachelor of Technology - BTech at Cochin University of Science and Technology
