Shibin Bose Kavara — Software Engineer

 Experience with leading a team, interaction with customers and handling multiple projects at the same time.  Experience of full product life-cycle of FPGA SoC/IP; starting from architecture definition, RTL design, Firmware operations, Implementation, simulation, block design and validation.  Experience with Low Power subsystem design.  Experience with Video input/output and video enhancement SoC/IP.  Experience with Processing In Memory (PIM) design for DRAM memories (DDR4 & LPDDR5)  Experience with different Cache Controller architecture and implementation (NVDIMM-P & LPDDR5)  Experience with developing a Security CPU subsystem with its Peripherals and Countermeasures.  Experience with Timing constraints and timing closure.  Experience with CDC & RDC in Design and Lint checks.  Experience with Prime Power based power estimation of SoC/IP.  Experience with Spyglass DFT checks for SoC/IP.  Experience with ASIC Back End flow with Floor Planning, Power Planning and Routing for foundry TestChips.  Experience with STA, IR analysis and design Routability analysis for foundry TestChips.  Experience with 28nm TestChip RTL to GDS.  TestChip design and test vector pattern generation for Memories and Standard cells for silicon testing. RESPONSIBILITIES :- FPGA/ASIC Architecture Design, Micro Architecture, RTL Design, Lint, Simulation, Verification, Testing, Validation, Power Estimation, Design Documentation LANGUAGES :- VHDL, Verilog, System Verilog Shell/Perl Scripting, C/C++. TOOLS :- Xilinx ISE, Vivado, Synplify Pro, Lattice ispLEVER, Reveal Logic Analyzer. Synopsys ICC, Synopsys Design Compiler, ModelSim, Cadence NCVerilog, Synopsys Verdi. Prime Time/Prime Power, Spyglass (Lint/DFT/CDC), AscentLint, Jasper (SEC/FPV), VC Static (RDC), Apache RedHawk. Xilinx SDK, Microsoft Visual C++, Lattice LCD Pro, VMS PROTOCOLS :- I2C, SPI, AMBA (AXI4, AXI3, AHB, APB, AXI4-Stream), Wishbone, UART, DDR4 & LPDDR5 (limited), NVDIMM-P, Gen-Z

Stackforce AI infers this person is a highly skilled ASIC and FPGA design engineer with extensive experience in semiconductor technology.

Location: Bangalore Urban, Karnataka, India

Experience: 15 yrs 6 mos