Sahil Kapoor

Engineering Manager

Cupertino, California, United States13 yrs 5 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in RTL synthesis and circuit design.
Led clean chip tape-out for advanced technology nodes.
Awarded for contributions to microcontroller software teams.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in RTL synthesis and physical design.

Contact

Skills

Core Skills

Rtl SynthesisCircuit DesignEdaTiming AnalysisFunctional ValidationHardware DesignPhysical Design

Other Skills

ASICApplication-Specific Integrated Circuits (ASIC)Auto QA Tool DevelopmentAutomated TestingC++CCS Noise Model AnalysisCMOSCTS planningCadence VirtuosoComputer ArchitectureDigital Circuit DesignEmbedded SystemsHardware ArchitectureIR/noise closureLEC

About

CPU Implementation Manager at Apple Inc. My core expertise are: RTL synthesis, micro-architectural feasibility study, Circuit Design, floorplaning, STA/timing closure, power closure, placement and routing, CTS planning, IR/noise closure, LEC, logic ECO implementation etc for a clean chip tape-out.

Experience

Apple

2 roles

Engineering Manager - CPU Design Implementation

Promoted

Oct 2022 – Present · 3 yrs 5 mos

CPU Implementation Engineer

Jun 2014 – Oct 2022 · 8 yrs 4 mos

RTL synthesis, micro-architectural feasibility studies, floorplaning, STA/timing closure, power closure, placement and routing, CTS planning, IR/noise closure, LEC, logic ECO implementation etc for a clean chip tape-out. Worked on leading edge technology nodes.

RTL synthesismicro-architectural feasibility studyCircuit DesignfloorplaningSTA/timing closurepower closure+5

Intel corporation

Graduate Student Intern

Jun 2013 – Dec 2013 · 6 mos · California

Development of Auto QA Tool for Library Models : Developed an automation tool for Quality Analysis of emerging Library Models. This benchmarks and aids library model enhancement by calculating the sensitivity of PrimeTime results wrt library attributes and timing models.
CCS Noise Model Analysis: Developed an algorithm to analyse CCB partitions for a standard cell and studied the impact of Pin/Arc based modelling options on the accuracy of CCS Noise Models.
Sensitivity Analysis of NLDM and CCS Timing/Noise Models : Identified the tables/attributes in library models that impact Prime Time results.

Auto QA Tool DevelopmentCCS Noise Model AnalysisSensitivity AnalysisEDATiming Analysis

Freescale semiconductor

Design Engineer

Jun 2011 – Jul 2012 · 1 yr 1 mo · India

Performed functional validation of various design IPs. Developed test-cases for automated testing
which set a baseline for automated regression flows.
Experience with hardware and system level architecture and board bring-up experience.
IPs validated - IIC, SPI, QuadTimer, CAN, MPU (Memory Protection Unit), UART, DMA, High Speed Comparator (Digital), PDB (Programmable Delay Block), ADC, DAC.
Worked on developing the "Next Generation Home Automation System". Involved in conceptual design and integrating applications on one platform.
"Winning Starts Here" award for providing support and solutions to Microcontroller software teams

Functional ValidationAutomated TestingHardware ArchitectureSystem Level ArchitectureHardware Design

St microelectronics

Design Intern

Dec 2010 – Feb 2011 · 2 mos

Worked with the Physical Design Team to study the impact of Non-Critical Block placement on the performance of Crypto Processors.
Implemented the Multi-Threshold CMOS technique to minimize leakage power and achieve timing closure.

Physical DesignMulti-Threshold CMOSTiming Closure