Feb 2019 – Nov 2022 · 3 yrs 9 mos

• Flow and Methodology development for custom physical design on Atom core CPU for Floorplan, Power Grid, Placement, Signal Routing, DFM, and Signoff, Block level assembly.
• Enabling Incremental PDK, Custom track creation, Custom power grid and PV flows
• Skill Automation, TCL, and shell scripting for custom tools setup for design engineers.
• Enabling tool for designers and mask designers, Trailblaze new tool to improve the productivity of the team.
• Perform technical evaluations of EDA tools and provide recommendations.
• Work with EDA vendors to resolve tool issues and bugs and give specification to develop macros
• Provide documentation, training, and support.
• Support/Develop custom trunk, detail router, metal fill, via fill, cell fill insertion, via coloring, custom power grid generation and DRC/LVS/DFM (at block and partition level)
• Tools:
• in/outside PDK tech enablement for backend tools, Virtuoso VXL/EXL, Custom Compiler, Intel in house tools, Calibre tool suites, ICV.

Feb 2019 – Nov 2022 · 3 yrs 9 mos

• Partition Integration for Atom CPU core which includes synthesis, floor planning, place, and route, cts , locate the critical path, congestion analysis, signoff (timing/EM/IR/formal).
• working on aggressively optimizing for PPA.
• Timing closure, correlation analysis, SDC generations, macro, and port placement
• RTL2GDSII

Aug 2018 – Dec 2018 · 4 mos · Minneapolis, Minnesota

• Department of Computer Science

May 2018 – Aug 2018 · 3 mos · San Francisco Bay Area

• Custom CAD | Virtuoso CAD | Cadence SKILL | Python | Perl | Unix | Batch Mode Runs | Virtuoso VXL | SKILL GUI
• GUI and Batch mode tool to report and improve the VXL compliance at the TOP hierarchical design used by Integration Manager, Block Level owner and Layout Designers downstream the automation provided by native Cadence tools.

Jan 2017 – Sep 2017 · 8 mos

• Test Chip Designs for Advance Nodes
• dealing mostly with Thin Film Resistor , RDAC, Resistors and MFCs
• Automation of Testchip layout design using Cadence Skill language

Sep 2015 – Dec 2016 · 1 yr 3 mos

• Awarded Intel Recognition award for high-quality layout work
• Top five idea finalist in Intel Maker Lab challenge
• Dealing with the Layout of PLL, LDO, and IDV at lower technology nodes.
• responsible for the creation of bottoms-up Chip design including but not limited to cell and block-level custom layouts, FUB level floorplans.
• Standard cell library methodology and design rules executing Physical verification and fixing the DRC's, LVS and densities.

Jun 2015 – Jul 2015 · 1 mo · Bengaluru Area, India

• Design and Verification of Electronic Design and System using System Verilog
• Creating Verification Environment for 16-bit LC3 Microcontroller using System Verilog.
• The main aim of the project was to create a verification environment and verify the various stages of the pipelined and un-pipelined version of LC3 Microcontroller using System Verilog on Questa Simulator provided by Mentor Graphics
• Complete Integration of LC3 ASIC was done using Golden Model and Assertions, a Test bench was made Modular using object-oriented programming to provide full functional coverage.

Nov 2014 – Jun 2015 · 7 mos · Bengaluru Area, India

• Was Responsible for Coding of a Value-Added Functions. set the threshold of a few important parameters and checking the response on Hardware simulator.
• Also understanding the customer requirement and translating in Block Diagram and Implementing the Design.
• Component Developer

Jul 2012 – Jun 2013 · 11 mos · Kharghar , Navi Mumbai

• Lecturer for Basics of Electrical and Electronics Engineering( BEEE ), Antenna Wave Propagation (AWP), Electromagnetic Wave Theory (EWT) theory and Micro-controller /Processor Lab sessions

Jun 2011 – Aug 2011 · 2 mos · Mumbai Area, India