Manikanta Gummadidala

Software Engineer

Bengaluru, Karnataka, India11 yrs 4 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Over 11 years of experience in ASIC verification.
  • Led verification for multiple complex SOC projects.
  • Expertise in UVM and low power verification methodologies.
Stackforce AI infers this person is a highly skilled ASIC Design Verification Engineer with extensive experience in complex SOC projects.

Contact

LinkedIn

Skills

Core Skills

Asic Design Verification

Other Skills

100GB Ethernet Protocol4G Modem5G Modem8051 MicrocontrollerAnalog Circuit DesignAudio DataBOOTROMC languageCDCCadenceCadence VirtuosoCircuit DesignComputer ArchitectureCoverage GenerationDebugging

About

Full-time MTech in VLSI ( + ) 11 + years of experience in functional verification ASIC verification at SOC level ,Subsystem Level and IP level. worked on 25 complex SOC's - ( Ethernet SOC ,4GModem SOC,5GModem SOC,Tablet SOC ,Automotive SOC's, Mobile SOC's) I am Looking for Dynamic position (senior manager in verification domain) where I can effectively contribute my Knowledge and skills towards full fledged growth of the Organization with utmost sincerity and I am self-confident, hardworking individuals a strong flair to accept Challenging opportunities. Skill Set: Software Programming languages : C,C++ Hardware Programming Languages: Verilog, System Verilog Bus Protocals : APB , AHB , AXI AUDIO Protocals: I2S,PCM,Soundwire Communication/Networking Protocal : ETHERNET , USB 2.0/USB3.0, USB 3.1 Gen2 storage protocals : EMMC (3.1) , UFS(3.0/3.1) Scripting Languages : Perl Methodology : UVM • Good Knowledge of UVM , Ethernet Protocol Low power Verification.. • Expertise on Testplan Creation, Execution, Code/Functional coverage closure, Performance Verification. • Worked on Constraint Random Verification Environment, System Verilog Based driver , monitor , checker development. • Implemented Functional Coverage From scratch. • Developed Entire Register Functional coverage class using Perl scripting. • Good Knowledge on computer Architecture. > Good problem solving and Debugging Skills.

Experience

Samsung electronics

3 roles

Senior Staff Engineer - ASIC Design Verification

Promoted

Mar 2021 – Present · 5 yrs

  • Currently working on SOC verification of USB, BOOTROM, UFS & MMC blocks ..
USBBOOTROMUFSMMCASIC Design Verification

Staff Engineer - ASIC Design Verification

Mar 2019 – Feb 2021 · 1 yr 11 mos

  • Leading Verification of USB and ETHERNET IP's at SOC level for Mobile SOC's , Automotive SOC's and Tablet SOC's
  • >Completing the project before deadlines with quality output.
  • >Verification plan and reviews with Design Team .
  • >Toggle Coverage for Sign OFF
USBETHERNETVerification PlanToggle CoverageASIC Design Verification

Associate Staff Engineer - ASIC Design Verification

Apr 2018 – Feb 2019 · 10 mos

  • worked on SOC verification of EMAC
  • for Automotive SOC's and Galaxy Series Mobile SOC's
  • >complete ownership of Module
  • >verification plan , Features verification
  • > Sign off from Design Team.
  • > Power Aware Verification , CDC and XPROP
  • >Delivering the Block with Quality output before Deadlines
  • >Good Team Player
EMACPower Aware VerificationCDCXPROPASIC Design Verification

Wafer space

2 roles

Design Engineer I - Senior ASIC Design Verification Engineer

Jul 2017 – Feb 2018 · 7 mos · Bengaluru Area, India

  • Client : Qualcomm
  • Qualcomm Tablet project
  • SOC Verification of Power Block (Always on subsystem) :
  • LOW POWER VERIFICATION:
  • worked on
  • entire SOC power management.(collapse/voltage min,sleep).
  • Language: c, systemverilog ,UVM methodology
  • Tool: VCS,MTI
Power BlockLow Power VerificationSOC Power ManagementASIC Design Verification

Design Engineer I - ASIC Design Verification Engineer

Jul 2016 – Jun 2017 · 11 mos · Bengaluru Area, India

  • Client :Qualcomm
  • SOC Verification of low power audio sub system (LPASS)- 4G modem project & 5G modem project :
  • Description:
  • Audio data (speaker/mic),voice calls over internet using AUDIO block.
  • In this project, I worked on ARM based SOC verification of LPASS sub system.
  • Language: c, systemverilog ,UVM methodology
  • Tool: VCS,MTI
LPASS4G Modem5G ModemAudio DataASIC Design Verification

Chelsio communications

2 roles

Member of Technical Staff - ASIC Design Verification Engineer

Jul 2015 – Jun 2016 · 11 mos · Bengaluru Area, India

  • >ASIC/SOC design verification.
  • >verification of 100GB Ethernet Protocal.
  • >understanding spec.
  • >create environment and writing test cases to verify the design using system verilog and perl scripting
  • >Debugging failures and filing bugs.
  • >Generating coverage(code and functional).
  • >had good knowledge on system verilog,verilog,perl scripting.
  • >had good knowledge on processor architecture,ASIC/SOC Design flow.
  • Languages: system verilog ,C,C++
  • Tools:VCS
100GB Ethernet ProtocolTest CasesDebuggingCoverage GenerationASIC Design Verification

Member of Technical Staff - ASIC Deisgn verification intern

May 2014 – Jun 2015 · 1 yr 1 mo · Bengaluru Area, India

  • >ASIC/SOC design verification.
  • >understanding spec.
  • >create environment and writing test cases to verify the design using system verilog and perl scripting
  • >Debugging failures and filing bugs.
  • >had good knowledge on system verilog,verilog,perl scripting.
  • >had good knowledge on processor architecture.
ASIC Design VerificationTest CasesDebugging

Education

Manipal Institute of Technology

Master of Technology (MTech) — Digital Electronics and Advanced Communication

Chalapathi Junior College,Lam,Guntur

Intermediate(10+2)

S.R.H School Mothadaka

ssc

Sri Krishnadevaraya University

Bachelor of Technology (BTech) — Electronics and Communication Engineering