Adarsh Santhosh — Product Engineer

DFT Engineer. Design for test: ATPG Lead for multiple projects @ Qualcomm(SAF, TDF, IDDQ), Spyglass(PLDRC - DFT/DFTDSM/clock and memory connections), LV(Tessent)MBIST, SCAN(Corebased DFT, DFT Stitch), Test constraints & STA, Formal verification(Conformal LEC SCAN and MBIST), Silicon Bring up and diagnosis. Design verification: System Verilog, UVM(Institute projects only), Assertion based verification for back-to-back ATPG patterns, OCC double pulse verification, IDDq power sensitive signals, FPGA prototyping(Institute projects only) Digital logic circuit design: TAP, OCC(On-chip clock controller), Streaming Scan Network(Minimal trial experience), EDT, LPCT, Test point insertion. Scripting: Python(Assertion based verification scripts for DFT), Linux, C++, vim, Tcl.

Stackforce AI infers this person is a DFT Engineer with expertise in ASIC design and verification.

Location: Bengaluru, Karnataka, India

Experience: 7 yrs 11 mos