DIVYA YADAV — Software Engineer
ASIC Design flow,Physical Designing, SoCs,RTL Synthesis,HDLs: VHDL, Verilog, System- Verilog,Programming languages: Basic knowledge of C, C++,Scripting language :Perl. Tools explored: HDL Tools: ModelSim, Xilinx project Navigator, EDA Tools: Synopsys Design compiler, Cadence encounter, Cadence –Virtuoso. TCAD: Silvaco TCAD(Atlas), Keil uVision 4.
Stackforce AI infers this person is a specialist in ASIC design and IoT solutions.
Location: Uttarakhand, India
Experience: 8 yrs 10 mos
Skills
- System On A Chip (soc)
- Vhdl
Career Highlights
- Expert in ASIC design and SoC development.
- Proficient in VHDL and RTL synthesis.
- Experience in IoT applications and microcontroller design.
Work Experience
Qualcomm
Staff Engineer (1 yr 4 mos)
Lead Senior Engineer (3 yrs)
Senior Engineer (2 yrs 2 mos)
BlueSemi R&D Pvt. Ltd.
Digital Design Engineer (1 yr 11 mos)
Aalto University School of Science and Technology
System on Chip development for IoT applications. (5 mos)
Education
Master's degree at Aalto University
VLSI Design at Dr. B R Ambedkar National Institute of Technology, Jalandhar ( PUNJAB)
