Krishnendhu u.n — Software Engineer
Experience Summary: • Overall experience of 6+ Years in FPGA RTL Design, Integration and Testing ,ASIC RTL signoff and software • Working as Senior Design Engineer for Cerium Systems. Client -Intel (From August 2020 to till date) • Worked as Senior Design Engineer for Cerium Systems. Client – Cisco Systems (From April 2018 to July 2020). • Worked as Design Engineer in Park Controls and Communications from December 2015 to March 2018. Technical Skills: • FPGA: Artix-7, Cyclone-IV, Cyclone-V,Microsemi Smartfusion • Microsemi Libero, Xilinx Vivado, Synplify pro, Altera Quartus 16, Qsys, Signal tap logic analyzer, SOPC Builder, ModelSim,Synopsis DVE,Spyglass Lint,Spyglass CDC, Design compiler, Fusion compiler, LEC ,ATPG and Caliber . • HDL Languages: VHDL, Verilog , RDL (Register descriptive language) • Software Languages: C (basic) and C++ • Protocol : Ethernet MAC, SGMII, MII, RMII ,UART, SPI, I2C, MDIO Clause-22, MDIO Clause-45
Stackforce AI infers this person is a skilled FPGA and ASIC design engineer with extensive experience in B2B technical environments.
Location: Bengaluru, Karnataka, India
Experience: 10 yrs 3 mos
Skills
- Fpga
- Rtl Design
Career Highlights
- 6+ years of experience in FPGA and ASIC design.
- Expertise in VHDL and Verilog for RTL coding.
- Proven track record with major clients like Intel and Cisco.
Work Experience
Intel Corporation
ASIC Design Engineer (6 yrs 8 mos)
Cisco
FPGA Design Engineer (1 yr)
Cerium Systems
Senior Design Engineer (8 yrs)
Park Controls & Communications (P) ltd.
RTL Design engieer (2 yrs 3 mos)
Education
Bachelor of Technology - BTech at Cochin University of Science and Technology
at higher secondary
at High school
