Prabhat Jain

DevOps Engineer

Austin, Texas, United States14 yrs 11 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in SoC performance architecture and memory systems.
Led multiple high-impact projects in semiconductor industry.
Strong background in performance evaluation and debugging.

Stackforce AI infers this person is a Semiconductor Performance Architect with expertise in memory systems and SoC design.

Contact

yoprabhat1@yahoo.com LinkedIn

Skills

Core Skills

Memory System And Cache CoherencyComputer ArchitectureMemory ControllersPerformance Evaluation Of SystemsSystem On A Chip (soc)Soc Performance ArchitecturePerformance AnalysisData Fabric ArchitectureProcessor Core ArchitectureComputer SciencePower Consumption Analysis

Other Skills

AlgorithmsBottleneck AnalysisBottleneck analysisCC++Collaboration with teamsDebuggingDynamic Random-Access Memory (DRAM)Evaluating performance featuresHigh Performance Computing (HPC)L2 Cache ArchitectureLPDDR6 and LPDDR5x memory technologiesMemory Hierarchy DesignMemory hierarchy designMicroprocessors

About

Computer Architect with a background in memory system and SoC performance - caches, coherence, on-chip interconnects, main memory

Experience

Samsung semiconductor

SoC Memory Controller Performance Architect

Feb 2023 – Present · 3 yrs 1 mo · Austin, Texas, United States · On-site

Worked on the main memory controller performance architecture for Samsung Exynos SoCs, used in the flagship Samsung Galaxy phones. Worked on LPDDR6 and LPDDR5x memory technologies. Responsibilities included performance modeling, feature development, analysis, debugging and evaluation

Dynamic Random-Access Memory (DRAM)Memory ControllersPerformance Evaluation of SystemsDebuggingMemory System and Cache CoherencyComputer Architecture

Arm

SoC Performance Architect

Feb 2020 – Apr 2022 · 2 yrs 2 mos · Austin, Texas, United States · Hybrid

Worked on performance analysis, performance projections, and bottleneck and scaling analysis
for various ARM reference design SoCs. Quantified the SoC level performance impact of various features and parameters like snoop filter size, memory-traffic based core throttling, core count, memory bandwidth, cache size, core frequency etc. This was used to provide guidance to business units and external partners for SoC design choices

Performance AnalysisBottleneck AnalysisScaling AnalysisComputer ArchitectureSystem on a Chip (SoC)

Amd

SoC Interconnect Performance Architect

May 2018 – Dec 2019 · 1 yr 7 mos · Austin, Texas, United States · On-site

Worked on the data Fabric architecture for all AMD products ranging from client to server. Responsibilities included modeling, evaluating and correlating/validating performance features. On the client side, worked on developing various QoS (Quality of Service) features, with particular focus on hard real time QoS. Worked on features to scale interconnect bandwidth support on server SoCs with ever increasing core count

Data Fabric ArchitectureQuality of Service (QoS)Performance EvaluationComputer ArchitectureSystem on a Chip (SoC)

Intel corporation

Processor Core Architect

Sep 2012 – Mar 2018 · 5 yrs 6 mos · Hillsboro, Oregon · On-site

Owned the L2 H/W Prefetcher architecture and the performance architecture of the entire L2 cache cluster on Knights/Xeon Phi (KNL - Knights Landing, KNH - Knights Hill) line of HPC/server products. That entailed developing features, modeling, debugging and analysis, performance validation and correlation while working closely with various stakeholders. Essentially, owning and delivering them from conception through product release. Silicon debugging was another aspect where issues affecting workloads were identified working alongside workload experts.

L2 Cache ArchitecturePerformance ValidationSilicon DebuggingComputer ArchitectureSystem on a Chip (SoC)

University of illinois at urbana-champaign

Research Assistant

Aug 2010 – Jul 2012 · 1 yr 11 mos

Worked on the DARPA funded UHPC project, along with Intel researchers, aimed at building an exascale machine. I explored power consumption of caches in multiprocessors and based on the study, proposed novel power saving techniques relevant for caches hierarchies in exascale systems. I also examined issues related to memory hierarchy design and the memory ISA

Power Consumption AnalysisMemory Hierarchy DesignComputer Science