Raghavendra JN

Director of Engineering

Bengaluru, Karnataka, India20 yrs 6 mos experience

Highly Stable

Key Highlights

18 years of ASIC verification experience
Proven track record in team building and management
Authored over 10 publications in the field

Stackforce AI infers this person is a semiconductor verification expert with extensive experience in ASIC design and verification.

Contact

Skills

Core Skills

Functional VerificationSocPower VerificationLow-power VerificationSub System VerificationVerification

Other Skills

SystemVerilogLow-power DesignPerformance VerificationPower AnalysisVerification of memory controllersPCIEVMMVeraOpen Verification MethodologyAXIAMBA AHBDDR3UVMSOC Low Power VerificationSub-system Verification

About

I joined Microsoft in June 2023 after 18 years in ASIC verification at Intel, Qualcomm, Xilinx, and Tundra, working across IP, sub-system, and SoC levels, with a focus on power and performance verification. I have authored over 10 publications and co-authored more than 8, presenting at major conferences. At Microsoft IDC, I am contributing to compute silicon development by building a team of exceptional engineers. I have a proven track record of building and managing high-performance teams that consistently deliver quality results on aggressive timelines. I have led and retained a global product development team through coaching, mentorship, performance management, and technical guidance.

Experience

20 yrs 6 mos

Total Experience

4 yrs 4 mos

Average Tenure

2 yrs 11 mos

Current Experience

Microsoft

Director

Jun 2023 – Present · 2 yrs 11 mos · Bengaluru, Karnataka, India · On-site

Leading an IDC Verification Team for Cloud Computing Development Organisation (CCDO) (Bangalore, Noida, and Hyderabad)

SystemVerilogFunctional VerificationSoCLow-power Design

Intel corporation

3 roles

HW Verification Director

Dec 2022 – May 2023 · 5 mos

Host IO Processor Verification @ Server Platform

Functional Verification

HW Verification Director

Promoted

Apr 2021 – Nov 2022 · 1 yr 7 mos

Custom and 3rd Party IP's, Sub System and SOC Verification @VTG

Functional Verification

Engineering Manager

May 2018 – Mar 2021 · 2 yrs 10 mos

Lead the development and verification efforts for First generation Imaging and AI centric ARM based SOC along with multiple Image Processing Unit skews for Intel CCG chipsets.
Area's : Functional, Power, Performance, Security, DFD, GLS, Test Vectors, Validation Support.

Functional VerificationPower VerificationPerformance Verification

Qualcomm

3 roles

Senior Staff Engineer / Manager

Dec 2017 – Apr 2018 · 4 mos

Lead low Power Verification for complete Mobile SOC’s with 120+ Power domains, multiple voltage and clock domains. Sub-system verification efforts for SOC Power Management for SDM chips

Low-power VerificationSub-system Verification

Staff Engineer / Manager

Dec 2015 – Nov 2017 · 1 yr 11 mos

Lead the Sub System Verification efforts and Power Analysis for Premier System cache based LPDDR3/4 DDR SS of Qualcomm chipsets MSM8998 and SDM845.

Sub System VerificationPower Analysis

Senior Lead Engineer

May 2013 – Nov 2015 · 2 yrs 6 mos

Lead the Sub System Verification efforts and Power Analysis for LPDDR3/4 DDR SS of Qualcomm chipsets MSM8916,8996.

Sub System VerificationPower Analysis

Xilinx

2 roles

Lead Verification Engineer

May 2011 – Apr 2013 · 1 yr 11 mos

Verification lead for multi-port PCDDR4, PCDDR3 and LPDDR3 memory controllers and Physical layer verification for Vertex, Kintex and ZYNQ product families

Verification of memory controllersVerification

Senior Design Verification Engineer

Dec 2008 – Apr 2011 · 2 yrs 4 mos

Verification on multi-port PCDDR3 and LPDDR3 memory controllers and Physical layer verification for Vertex, Kintex and ZYNQ product families

Verification of memory controllersVerification

Tundra semiconductor

Design Engineer

Feb 2005 – Nov 2008 · 3 yrs 9 mos

Worked on PCIE register modelling, test plan, test bench architecture and verification component development for PCIE Internal Switch fabric using System Verilog on VMM methodology.
Reference model development for PCIE Transaction layer and complete Error model for multi-port PCIE switch using Vera on RVM methodology
Verification of Transaction Layer Unit, Error Handling Unit, Flow control, Data link layer and Configuration Space Register for PCIE to PCI/PCIX bridges
Conducted several technical sessions in the company, Presentation on Low Power methodology and Verification challenges, UPFs, Usage of MVSIM and MVRC, Tundra Verification flows, Tutorial on Object Oriented programming and VERA
Areas of Expertise : PCI Express, PCI Express Switch, PCI Express to PCI/PCIX Bridge, PCI, PCIX, Verilog, Vera, OVM, OVM RGM

PCIESystem VerilogVMMVeraVerification