Pranshu Garg

Software Engineer

Los Angeles, California, United States6 yrs 6 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expertise in performance verification at NVIDIA.
Research on innovative memory architectures for ML applications.
Experience in optimizing analog design for neuromorphic chips.

Stackforce AI infers this person is a specialist in semiconductor design and verification with a focus on advanced memory architectures.

Contact

pranshugarg23@gmail.com LinkedIn

Skills

Other Skills

ANSYSAdvanced Design System (ADS)ArduinoBashBusiness Model CanvasC (Programming Language)CadenceCustomer DevelopmentHFSSLaTeXMatlabMixed-Signal IC DesignPresentation SkillsProduct DevelopmentPython (Programming Language)

About

Working with the Performance Verification for the Streaming Multiprocessor Unit at NVIDIA. Always interested in talking about entrepreneurial opportunities, music (learning drums myself), playing team sports of any kind, travel, and am a personal finance nerd.

Experience

Nvidia

2 roles

Senior Verification Engineer

Promoted

Mar 2024 – Present · 2 yrs · Santa Clara, California, United States · On-site

Verification Engineer

Jun 2021 – Mar 2024 · 2 yrs 9 mos · Santa Clara, California, United States · On-site

Polyarch research group ucla

Graduate Student Researcher

Oct 2020 – Jun 2021 · 8 mos · Los Angeles, California, United States

Research on integrating a new memory idiom, Buffets, into the group's existing programmable ASIC architecture. Potential to improve performance by 1.5x for ML loads in 1/3rd memory area.

Ucla integrated sensors laboratory

Graduate Student Researcher

Sep 2020 – Jun 2021 · 9 mos · Los Angeles, California, United States

Research on integrating memory and logic into ultra-low power wireless implants to enable next-gen patient monitoring, pacemaking, and resuscitation functionalities.
Working on a business model to launch very high-frequency (THz) sensing and imaging technology to replace expensive and bulky laser technology used today.

Ucla henry samueli school of engineering and applied science

2 roles

Gradute Teaching Associate

Promoted

Jun 2020 – Jun 2021 · 1 yr

Graduate Teaching Assistant

Oct 2019 – Jun 2020 · 8 mos

Texas instruments

Analog Design Engineer

Jun 2020 – Sep 2020 · 3 mos · Santa Clara, California, United States

Brought up the existing full hardware stack testbench for Partial Loop Unrolled DFE PAM4 receiver from a dysfunctional state in cadence mixed-signal environment
Introduced macromodeling technique using ideal analogLib (spectre or VerilogA models) for SSLMS algorithm design; reduced simulation time from 2 weeks to 2 hrs, the design cycle is not bottlenecked by RTL design, making changes to the algorithm becomes very easy
Constructed understanding on first & second-order changes in DFE coefficients governed by mathematical expressions
Pointed a major weakness in algorithm and architecture; verified results with Cadence Mixed-Signal RTL Level sims

Center for heterogeneous integration and performance scaling (chips), ucla

Graduate Student Researcher

Oct 2019 – Apr 2020 · 6 mos · Greater Los Angeles Area

Responsible for optimizing the performance of the charge integrator (neuron) circuit in a neuromorphic chip
Conducting Power and Signal integrity analysis for verification of chip functionality

Texas instruments

Analog Design Engineer

May 2018 – Jul 2018 · 2 mos · Bengaluru Area, India

Project: Effect of Compensation on Output Impedance of OPAMP. Derived models of commercial amplifiers and developed explanations of output impedance behavior based on circuit parameters. Additional Project: Comparison of proprietary processes of TI for use in OPAMP design.
Full-time job offer for performance during the intern.