Abhishek Sourya

Software Engineer

Noida, Uttar Pradesh, India6 yrs 10 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expertise in SoC physical design and timing closure.
Proven track record in RF design and simulation.
Strong problem-solving skills in complex design environments.

Stackforce AI infers this person is a Physical Design Engineer specializing in SoC and RF design within the semiconductor industry.

Contact

Skills

Core Skills

Timing ClosureFloorplanningRf Design

Other Skills

Place & RouteProblem Solvingcadance InnovusANSYS HFSSProduct DemonstrationFloor PlansRedhawkflowtracerETXTCLLTEElectronic EngineeringElectromagneticsCommunicationExpedition PCB

About

Working on SoC physical design at Qualcomm with 3+ years of experience. I have expertise in floorplanning, PnR, CTS and timing closure. I am having experience of working on SoC level and Hardmacro level with adaptation to translate the learning quickly. I have worked on/with Formality verification, low power conformal checks, PDN checks, PV checks, Timing checks team. Worked proactively in multiple tapeout with converging all signoff checks on SoC.

Experience

6 yrs 10 mos

Total Experience

3 yrs 5 mos

Average Tenure

5 yrs 8 mos

Current Experience

Qualcomm

3 roles

Senior Physical Design Engineer

Promoted

Jan 2025 – Present · 1 yr 4 mos

1. Analyzed timing violations that are due to IO timing assertion and communicated to timing engineer.
2. Used useful concepts of skew to fix timing violations.
3. performed repeater analysis and modified the repeaters based upon the feasibility to fix interface timing paths.
4. analysed DRC shorts and collaborated with physical verification team to work on the fix.
5. ananlysed and cleaned formaility verification and conformal low power checks.
6. collaborated with PDN teams to ananlyse and fix the high resistance supplies, secondary/primary opens and IR.

Place & RouteTiming Closure

Physical Design Engineer

Promoted

Jan 2022 – Dec 2024 · 2 yrs 11 mos

1. expertise in working on floorplan, PnR, CTS, Routing and timing closure.
2. Comprehensive knowledge in physical design implementation floorplan.
3. worked on timing and congestion aware placement with working on sanity checks for netlist and SDC constraints.
4. mitigated multiple flow issues for better and quicker convergence of the database.

Problem Solvingcadance InnovusFloorplanning

Associate Engineer

Jul 2020 – Dec 2021 · 1 yr 5 mos

Worked on multiple design and implementation of RF Card design. Key learnings and deliverables for my current positions are:
1. Schematic design for RF card
2. Layout review/RF Trace breakout design for RF Transceiver
3. RF trace simulation using Ansys
4. RF matching for load and source
5. 3GPP testing for cellular testing (GSM,WCDMA,LTE,nR)
6. Worked with PA, LNA, Diplexer, Antenna tuner, coupler, NB/WB filter

ANSYS HFSSProblem SolvingRF Design