Vishad Viplav

Software Engineer

Ghaziabad, Uttar Pradesh, India7 yrs 4 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in CPU physical design and implementation.
Proven track record in high-performance semiconductor projects.
Strong collaboration with cross-functional teams.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in CPU physical design and RTL methodologies.

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Skills

Core Skills

Physical DesignRtl DesignAnalog Design

Other Skills

ARMv9CPU PHYSICAL DESIGNECO phaseESD setupGDS deliveryGPIO designIntegrated Circuits (IC)Level shiftersPDV issuesPPA recipesPhysical Design VerificationPhysical ImplementationPython (Programming Language)RTLRTL Coding

Experience

Sifive

Senior Engineer II

Mar 2022 – Present · 4 yrs · Bengaluru, Karnataka, India · Hybrid

CPU PHYSICAL DESIGN
Physical Implementation of Frontend Unit (Instruction Fetch + Rename/Dispatch) of a next generation high performance P Series CPU Core
Active Engagement with RTL, architecture and performance teams to resolve timing issues for critical paths and area optimisations - extreme frequency targets
Understanding the uArch of the block in detail and detailed analysis of paths to pin-point the exact issues and scope of optimisation
Micro Architecture improvement ideas for various structures and paths which got implemented later on
Refinement of PPA recipes for advanced TSMC N5 and N3 nodes to get frequency-power push for the block
Contribution in floor-planning of the entire CPU Core based on arch understanding
Implementation of P670 Core for a wearable product tapeout
Co-led the design convergence on the latest Samsung node within very strict timelines (~3 months)
Involved in performance-area tradeoffs and SRAM selections, engaged with RTL teams to fix timing paths
Contributed to frequency push of P670 in TSMC N5 node and the PPA optimisations

CPU PHYSICAL DESIGNPhysical ImplementationRTLtiming issuesarea optimisationsuArch analysis+4

Google

Silicon Engineer

Jul 2019 – Mar 2022 · 2 yrs 8 mos · Bengaluru Area, India

CPU PHYSICAL DESIGN
Involved in 3 SOC tapeouts during the tenure
ARMv9 based High Performance Core
Co-owned the physical implementation of the full CPU core in Samsung 4nm advanced nodes
Delivered the final GDS before schedule meeting both frequency (2.5Ghz+) and power targets
Collaborated with mutiple sign-off teams to implement correct by construction approaches enabling a shorter ECO phase
Analysed critical paths in detail to come up with efficient floorplan, macro placement, bounds and custom PNR recipe
Received spot bonus and multiple peer bonuses for the implementation efforts
ARMv8 based CPU Sub System
Drove floorplanning activities and base PDV issues cleanup for high performance - efficieny CPU core
Delivered RTL2GDS independently for an interface block - had multiple power domains and DFT modules/wrappers
Drove PDV and EMIR closure of L3 block and contributed to its timing closure
Received spot bonus and multiple peer bonuses for the implementation efforts
ARMv8 based CPU Core
Owned RTL2GDS delivery of an interface block - first exposure to Physical Design
Quick Ramp-up on PnR, synthesis and STA tools along with Tcl scripting and PD methodologies
RTL Activities - CPU Sub System
Involved in RTL Integration for CPU Cluster for 3 SoC Tapeouts
Owned Memory Integration for many blocks, SRAM selection based on architecture
requirement and PPA
Automated the memory integration process - reduced the turnaround time from 4-5 days to few hours (mix of python and Tcl)
Handled RTL2RTL LEC verification and its debug
Collaborated with MBIST and UPF teams to make incremental changes in RTL based on the requirements

CPU PHYSICAL DESIGNSOC tapeoutsARMv9GDS deliveryECO phasefloorplan analysis+4

Texas instruments

Analog Intern

May 2019 – Jul 2019 · 2 mos · Bengaluru, Karnataka, India

Created complete Schematic for a 3.3V/5V Bi-directional GPIO for 50 Mhz frequency and 5pF load
Designed various elements like Level up/down shifters, Schmitt Triggers and Drivers and ESD setup
Optimised the GPIO for impedance, duty cycle across all PTV corners

Schematic designGPIO designLevel shiftersSchmitt TriggersESD setupAnalog Design