Manoz T

Product Engineer

Bengaluru, Karnataka, India20 yrs 2 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • 14+ years in Physical Design Engineering.
  • Expert in multiple block level physical design.
  • Proficient in Cadence design and verification tools.
Stackforce AI infers this person is a Semiconductor Design Engineer with extensive experience in Physical Design and Verification.

Contact

LinkedIn

Skills

Other Skills

Physical DesignSoCASICPhysical VerificationTimingLVSDRCVLSIRTL DesignCadenceEngineeringVerilogTCLStatic Timing Analysis

About

Physical Designer:, 14+ years of experience as a Physical Design Engineering. Currently working as Block Level Manager at Samsung India Research, Bangalore. Worked as Contingent Worker for Intel Corporation Experience in handling Multiple Block Level Physical Design - Subsystem planning, Data Preparation, FloorPlan, Synthesizing PowerPlan, CTS, Timing Optimization, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis. Experience in handling Top Level ECO works – functional metal eco, Worked on 10n, 14n, (finfet) , 28n,32nm, 45nm, 65nm, 65nm, 130nm Technologies Specialties: Proficient in major design and verification tools from Cadence like SOC Innovus implementation System , Genes, QRC, CeltIC, Voltage Storm, and Common Timing Engine. Synopsis: Design Compiler,ICCII & PT, Mentor Graphics Nitro(APR),caliber IBM: ChipBench,ChipEdit IBM: theGuide, chipBench, chipedit, etc..

Experience

20 yrs 2 mos
Total Experience
3 yrs 8 mos
Average Tenure
7 yrs 11 mos
Current Experience

Intel corporation

SoC Design Engineer

Sep 2020 – Present · 5 yrs 7 mos · Greater Bengaluru Area

Tessolve

Staff Engineer

May 2018 – Present · 7 yrs 11 mos · Bangalore

Cadence design systems

Lead Application Engineer

Jun 2017 – Jan 2018 · 7 mos · Bangalore

  • Worked as Lead Application Engineer, supported Global Foundries

Mentor graphics

Application Engineer

Oct 2012 – Jun 2017 · 4 yrs 8 mos · Hyderabad Area, India

Infotech

Physical Designer

Jun 2009 – Oct 2012 · 3 yrs 4 mos

  • Worked on projects at 45 nm 5 blocks with different sizes.

Time2market

Physical Design Engineer

Aug 2006 – May 2009 · 2 yrs 9 mos · Hyderabad, Telangana, India

Indian institute of technologies

R&D Engineer

Aug 2005 – Jul 2006 · 11 mos · Kanpur Area, India

  • Research on display technologies using organic materials

Education

Indian Institute of Technology, Kanpur

Master of Technology (M.Tech.)

Jan 2003 – Jan 2005

Osmania University

Bachelor's Degree — ECE

Jan 1996 – Jan 2000

CELT

Stackforce found 100+ more professionals with Physical Design & SoC

Explore similar profiles based on matching skills and experience

Pritender Singh

Pritender Singh

Principal Design Engineer

at TSMC

Kanata, Canada17 yrs 4 mos exp
ASICEmbedded SystemsVLSI
Ramesh Halli

Ramesh Halli

Senior Department Manager

at MediaTek

Bengaluru, India21 yrs 2 mos exp
Gaurav Goyal

Gaurav Goyal

Technical Director

at NXP Semiconductors

Bengaluru, India17 yrs 8 mos exp
Pankaj Verma

Pankaj Verma

Design Verification Lead

at Accenture

Bengaluru, India25 yrs 2 mos exp
Functional Verification
Swetha Gunda

Swetha Gunda

Senior Technical Manager

at AMD

Bengaluru, India18 yrs 6 mos exp
Swapnil Vats

Swapnil Vats

Senior Staff Engineer/Manager

at Qualcomm

Noida, India14 yrs 6 mos exp
Kiran Patel

Kiran Patel

Technical Program Manager

at Intel Corporation

Bengaluru, India24 yrs 9 mos exp
Project ManagementVLSI
Bharath TV

Bharath TV

Senior Engineering Manager

at NVIDIA

Bengaluru, India21 yrs 1 mo exp