Arun V. Ananthanaryan

CTO

Hyderabad, Telangana, India15 yrs 3 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in GPU Performance Modeling and Architecture.
Proven leadership in next-generation semiconductor projects.
Strong background in Machine Learning and VLSI design.

Stackforce AI infers this person is a semiconductor engineering expert with a focus on GPU performance and architecture modeling.

Contact

Skills

Core Skills

ArchitecturePerformance ModelingArchitecture ModelingHigh Performance Computing (hpc)Hardware Design

Other Skills

Hands-on Technical LeadershipRust (Programming Language)CommunicationC/C++CoachingProgrammingCache ManagementProblem SolvingInterviewingComputer ScienceC++MentoringMicroarchitectureMachine LearningSystem Architecture

About

Experienced Principal member of technical staff with a demonstrated history of working in the semiconductors industry. Currently leading Architecture/Performance Modelling with a past history in RTL development/integration, RTL verification/debug, FPGA prototyping of Application-Specific Integrated Circuits (ASIC) designs mainly in the Video/Graphics-Compute/ML-Inference space. Strong engineering professional with a Diploma focused in VLSI Logic Design from Veda IIT, Hyderabad and a Bachelors in E.C.E from NIT, Trichy.

Experience

Amd

4 roles

Principal Member of Technical Staff

Promoted

Jul 2024 – Present · 1 yr 8 mos

Leading next generation Architecture model feature development for next generation Instinct products.
Lead architecture feature scoping, model planning and execution for Graphics Compute IP
Own end to end performance reporting for real world workload GPU kernels on architecture model
Develop S/W methodologies that speed up and left shift kernel bring up on arch. model

Hands-on Technical LeadershipArchitecturePerformance modeling

Senior Member Of Technical Staff - Silicon Design Engineer

Jul 2022 – Jul 2024 · 2 yrs

Lead next-generation Compute Model development.

Rust (Programming Language)CommunicationC/C++CoachingHigh Performance Computing (HPC)Programming+14

Member Of Technical Staff - Silicon Design Engineer

Promoted

Jul 2020 – Jul 2022 · 2 yrs

Compute Workload Performance Modelling & Verification:
Lead next generation Compute IP architecture model development
Working closely with Compute Application Performance group to develop innovative performance triage methodology on C++ performance models
Architect and lead development of performance model regression infrastructure to run, record and visualize compute application performance across the group

CommunicationC/C++ProgrammingArchitecture ModelingCache ManagementProblem Solving+7

Senior Silicon Design Engineer

Oct 2017 – Jul 2020 · 2 yrs 9 mos

Designing reference behavioral and architecture models in C/C++ being used to verify various compute IP components
Developing and integrating configurable verification infrastructure using Python and C/C++ in effect accelerating bring up and verification of various IP components
Developed and coded test level firmware for a Compute IP with performance and configuration requirements

CommunicationProgrammingArchitecture ModelingCache ManagementProblem SolvingComputer Science+3

Lattice semiconductor

Senior Engineer

Jun 2015 – Sep 2017 · 2 yrs 3 mos · Greater Hyderabad Area

FPGA DSP Soft IP development:
Worked for Soft IP solutions team for company's bleeding edge FPGA line
Responsible for development of DSP Soft IP leveraging the FPGA's DSP core for Machine learning use cases
Worked with architecture team to custom tailor the DSP architecture to better suite Soft IP use case
Developed Soft IP from Specification to RTL
Automated preparation of Soft IP XML metadata file from Excel sheet input using Python

Hardware DesignProblem SolvingArchitectureScripting

Silicon image

Senior Engineer

Jan 2012 – Jun 2015 · 3 yrs 5 mos · Greater Hyderabad Area

HDMI IP Integration, Front end closure, Emulation and Verification:
Worked on Front end flow development including Lint, CDC, Synthesis and STA for company's HDMI1.4/2.0/2.1 IPs
Consistently closed CDC checks for HDMI RX IP deliverables
Worked on IC level RTL integration and bring up from digital IPs to Analog PHYs
Have experience in STA and Synthesis using Synopsys Prime-time and Design compiler
Worked with several teams to automate tasks using Python, often reduced design cycles for digital and analog teams
Performed FPGA Prototyping/Emulation bring up for HDMI RX IP's including industry first HDMI 2.1 RX IP on Xilinx Virtex 5/6/7 platforms
Experience in emulation bring up of several HDMI features such as HDCP 1.4 and 2.2, HDMI 1.4, 2.0 and 2.1 features such as 4k DSC core, multi-channel audio and other features
Worked closely with System engineering lab team and have experience in operating Video test pattern generators/analyzers from Quantum data, Video test pattern generators from Simplay Labs, board level debug using Tektronix Oscilloscopes and Chipscope debug using in house developed Xilinx platform

Hardware DesignProblem SolvingScripting

Soctronics

Engineer

Nov 2010 – Jan 2012 · 1 yr 2 mos · Greater Hyderabad Area

Worked on Lint, CDC, Synthesis flow bring up and flow development
Responsible for CDC checks closure for several video IP cores
Developed numerous automation in PERL and Python to extract target data from reports
Worked on RTL integration for several IP level systems

Hardware DesignProblem SolvingScripting