Tejaswi Y. — Software Engineer
RTL design engineer having 3+ year of Exp . I worked on multiple high speed peripheral interface like PCIE , CXL ,Ethernet protocol. and other AMBA protocol like AXI4, APB. I recently joined SOC integration team in Qualcomm as Senior Engineer .
Stackforce AI infers this person is a skilled RTL design engineer specializing in high-speed communication protocols.
Location: Noida, Uttar Pradesh, India
Experience: 4 yrs 9 mos
Skills
- Rtl Design
- Vhdl
- Cxl
- Axi
Career Highlights
- Over 3 years of experience in RTL design.
- Expertise in high-speed peripheral interfaces like PCIE and CXL.
- Currently a Senior Engineer at Qualcomm.
Work Experience
Qualcomm
Senior Engineer -RTL Design (1 yr 7 mos)
LOGIC FRUIT TECHNOLOGIES
Senior Research And Development Engineer (3 yrs 2 mos)
Education
Bachelor of Technology - BTech at Motilal Nehru National Institute Of Technology
