hemant kumar

Software Engineer

Bengaluru, Karnataka, India15 yrs 8 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in ASIC design and verification processes.
Proficient in multiple verification methodologies and tools.
Strong background in CPU and GPU verification.

Stackforce AI infers this person is a highly skilled ASIC verification engineer with extensive experience in semiconductor design.

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Skills

Core Skills

VerificationAsicCpu VerificationSocGpu

Other Skills

AMBA AHBAXIBus VerificationCCXL host controllerDMA EngineDenali memory modelsDesignware AHB UVM VIPFPGAFault injectionFunctional VerificationGIC600 VIPHSICLPDDR3ModelSim

About

Staff Engineer in the domain of RTL to GDSII flow in ASIC 2. Worked on synthesis, C Programming Language and power analysis of multiple chipsets using tools including Synopsys Design Compiler, Questasim and VCSIM 3. Have an experience in Synthesis & Design-for-Test (DFT), STA/SOC

Experience

Sifive

Senior Staff Engineer

Oct 2022 – Present · 3 yrs 5 mos · Bengaluru, Karnataka, India · On-site

Verification of vector processing unit on in order cores.
Verification of CXL host controller at subsystem level with CPU and coherent interconnect.

VerificationCXL host controllerVector processing unitASIC

Samsung

Senior Staff Engineer

Sep 2018 – Feb 2023 · 4 yrs 5 mos · Bangalore

CPU Verification: Bring up of GIC600 VIP. SPI/PPI/LPI verification with/without CPU. Basic coherency verification. CPU to DRAM request testing. CPU DVFS testing.
Bus Verification: All legal and ill-legal access. Performance, latency and Outstanding requests measurements. Request properties override. Parallel accesses from all masters to all slaves in the SoC.

CPU VerificationGIC600 VIPSPI/PPI/LPI verificationBus VerificationSoC

Nvidia

Senior Verification Engineer

Jun 2014 – Aug 2018 · 4 yrs 2 mos · Bangalore

Safety verification of GPU using Synopsis Z01X :
Created FIDM (fault injection and diagnostic manager) for redundant execution and machine check of GPU. Created fault simulation flow for GPU. Ran fault simulations for different IP's of GPU.
Verification of Floor sweeping logic for CPU, GPU and Computer vision logic at SoC.
Pre and Post silicon verification of Clocks logic in CPU:
Clocks routing in CPU cluster. Switching of clock source between different plls in CPU cluster. Clock gating for power saving. Automatic frequency and voltage switching based on CPU load.
Verification of security block in debug logic.
Verification of package connections with port connections.
Verification of SMMU using UVM environment.
Added verification components to emulate memory which responds to page table walk requests.
Wrote verification components to do random invalidations and sync using coherency channel of ACE interface

Safety verificationGPUFault injectionPre and Post silicon verificationVerification

Lsi corporation

ASIC DvDs Engineer 2

Apr 2013 – Jul 2014 · 1 yr 3 mos · Bangalore

Verificaiton of DMA Engine for Ethernet IP using Designware AHB UVM VIP.
Verification of memories with repair logic using UVM. Wrote function coverage.

VerificationDMA EngineDesignware AHB UVM VIPASIC

Qualcomm

Engineer

Jul 2010 – Apr 2013 · 2 yrs 9 mos

Verification of USB, HSIC using NSYS vip.
Verification of USB3 using NSYS vip.
Verification of DMA engine at SoC level.
Verification of LPDDR3 using Denali memory models.
Verification of debug logic in modem and verification of interrupt connectivity using assertions.

USB verificationHSICLPDDR3Denali memory modelsVerificationSoC