Praneet Vibhu B.

Software Engineer

New York, New York, United States6 yrs 3 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in CMOS chip design and FPGA implementation.
  • Proficient in machine learning and neural network applications.
  • Strong background in computational neuroscience and systems biology.
Stackforce AI infers this person is a Hardware and Software Engineer specializing in semiconductor and AI technologies.

Contact

Skills

Core Skills

Software DevelopmentHardware DesignMachine Learning

Other Skills

JavaCMOS chip designCadence VirtuosoFPGAConvolutional Neural NetworksSpike Time Dependent PlasticityComputer ArchitecturePythonVHDLResearchMatlabC++HTMLRNeural Networks

About

I aim to build hardware and systems based on neurocomputing. I have worked on CMOS chip design as well as System-on-chip (SoC) platforms. I have taken multiple courses involving machine learning and neural networks during my undergraduate and graduate courses of study. I have studied computational neuroscience and systems biology as well to further understand the functioning of the system which influenced neural networks, the Brain.

Experience

Amazon

SDE

Aug 2022Present · 3 yrs 7 mos · New York, United States

JavaSoftware Development

Capital one

Data Engineer/Python Developer - Contractor

May 2020Sep 2022 · 2 yrs 4 mos

Columbia university in the city of new york

2 roles

Research Assistant

Sep 2019Dec 2019 · 3 mos

  • Dense CMOS Chip Design, Lightwave Research Laboratory:
  • Designed a CMOS chip (TSMC 180nm technology) to drive a large optical phased array using Cadence Virtuoso
  • Designed the layout of the memory block and pad frame, and ran DRC, LVS, ERC and Antenna checks on the whole chip
  • Implemented a control block on a Cyclone IV FPGA to drive the digital inputs to the chip
CMOS chip designCadence VirtuosoFPGAHardware Design

Summer Research Assistant

May 2019Sep 2019 · 4 mos

  • Neural Acoustics Processing Lab:
  • Designed a feedforward Convolutional Spiking Neural Network for spoken digit recognition from TIDIGITS dataset
  • Applied a novel training method based on Spike Time Dependent Plasticity (STDP) synapse updates achieving 95% accuracy
Convolutional Neural NetworksSpike Time Dependent PlasticityMachine Learning

Samsung r&d institute india - bangalore private limited

Summer Intern

May 2017Jul 2017 · 2 mos · Bengaluru Area, India

Reliance jio infocomm limited

Summer Intern

May 2016Jul 2016 · 2 mos · Bengaluru Area, India

Education

Columbia University

Master of Science - MS — Electrical and Electronics Engineering

Jan 2018Jan 2019

Indian Institute of Technology, Bombay

Bachelor of Technology - BTech — Electrical Engineering

Jan 2014Jan 2018

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