S

Sridhar Venkatesh

Software Engineer

Bengaluru, Karnataka, India10 yrs 3 mos experience
Highly Stable

Key Highlights

  • Expertise in ASIC and FPGA design.
  • Proven track record in timing closure and methodology development.
  • Strong scripting skills supporting verification and software teams.
Stackforce AI infers this person is a highly skilled RTL Design Engineer in the semiconductor industry.

Contact

LinkedIn

Skills

Core Skills

AsicFpgaRtl Design

Other Skills

IP designSub system integrationflow/methodology developmenttiming closurescriptingsupport to verificationsoftware teamsmethodology developmentFPGA prototypingpartitionbring up of SoCsOTN IP optimizationtransceiversdata deskewingPnR

About

RTL Design Engineer with a demonstrated history of expertise in the ASIC Front end & FPGA design to bring-up cycle. Skilled in IP design, Sub system integration, flow/methodology development, timing closure, bring up, scripting and support to verification, software teams.

Experience

Google

RTL design engineer

Jun 2025 – Present · 9 mos · Bengaluru, Karnataka, India

IP designSub system integrationflow/methodology developmenttiming closurescriptingsupport to verification+3

Arm

Staff Engineer

Jun 2022 – Jun 2025 · 3 yrs · Bengaluru, Karnataka, India

  • DSU design team member.

Qualcomm

2 roles

Senior Lead Engineer

Dec 2021 – Jun 2022 · 6 mos

Senior engineer

Nov 2019 – Nov 2021 · 2 yrs

  • CPUSS RTL design engineer

Intel corporation

SoC design engineer

Jul 2018 – Nov 2019 · 1 yr 4 mos · Bengaluru, Karnataka, India

  • RTL design, methodology development for FPGA prototyping, partition, bring up of SoCs in multi slot, multi FPGA system
RTL designmethodology developmentFPGA prototypingpartitionbring up of SoCsRTL Design+1

Tejas networks

2 roles

Senior R&D Engineer

Promoted

Apr 2018 – Jul 2018 · 3 mos · Bengaluru, Karnataka, India

  • RTL design for OTN IP optimization, transceivers, data deskewing, PnR and lab bring up of multi FPGA, multi slot systems
RTL designOTN IP optimizationtransceiversdata deskewingPnRlab bring up+2

R&D Engineer

Jul 2015 – Mar 2018 · 2 yrs 8 mos · Bengaluru, Karnataka, India

Education

Madras Institute of Technology Campus

Bachelor's Degree — ECE

Jan 2011 – Jan 2015

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