Nikhil Jain

Product Engineer

Delhi, India18 yrs 3 mos experience
Highly Stable

Key Highlights

  • Expert in CXL and UCIe Verification IP development.
  • Strong background in memory technologies including DDR5 and HBM.
  • Proficient in Functional Verification methodologies.
Stackforce AI infers this person is a Semiconductor Verification Engineer specializing in advanced memory and interconnect technologies.

Contact

LinkedIn

Skills

Core Skills

Functional VerificationSystemverilog

Other Skills

AMBA AHBASICCadenceDDR5DRAMEDAEthernetFPGAHBMLinuxModelSimOpen Verification MethodologyRTL designSoCUVM

About

Design & Verification professional. Currently involved in development of CXL and UCIe Verification IP. Previously worked on Memories VIP, Ethernet VIP

Experience

Synopsys inc

2 roles

Principal Engineer , R&D Engineering

Promoted

Feb 2024 – Present · 2 yrs 1 mo · Noida, Uttar Pradesh, India · On-site

  • Working on CXL and UCIe Transactor

Senior staff R&D Engineer

Nov 2022 – Feb 2024 · 1 yr 3 mos · Noida, Uttar Pradesh, India · On-site

  • Working as Product Engineer for CXL VIP and UCIe VIP
SystemVerilogUVMDRAMDDR5HBMEthernet+1

Mentor graphics

5 roles

Principal Engineer

Promoted

Jan 2022 – Nov 2022 · 10 mos

  • Working on CXL 2.0/3.0 and UCIe

Lead member of consulting staff

Jan 2019 – Dec 2021 · 2 yrs 11 mos

  • Worked on DDR5, LPDDR5, HBM 2/2e
  • worked on CXL

Member of Consulting Staff

Aug 2015 – Dec 2018 · 3 yrs 4 mos

  • Worked on DDR2/3, LPDDR2/3/4, Wide IO 1/2, HMC v1 and v2, HyperFlash and Hyper RAM.
  • Currently working on NVMe Over Fabrics(both NVMe and Ethernet Side)

Lead Member Technical Staff

Promoted

Aug 2011 – Jul 2015 · 3 yrs 11 mos

Senior Member Technical Staff

Oct 2010 – Aug 2011 · 10 mos

Nsys design systems

3 roles

Team Lead

Apr 2010 – Sep 2010 · 5 mos

Senior Design Engineer

Promoted

Jul 2009 – Mar 2010 · 8 mos

Design Engineer

Jul 2007 – Jul 2009 · 2 yrs

  • nSys Verification Suite (nVS) family is the largest collection of Verification IPs available from a single source. Hundreds of ASIC, FPGA & IP developers are currently using the nVS family to benefit from widely accepted & proven BFM, Monitor, Assertions based Checkers and Test suites

Education

Guru Gobind Singh Indraprastha University

Bachelor of Technology (BTech)

Jan 2003 – Jan 2007

Kulachi hansraj model school

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