Gaurav Kumar Srivastava — Software Engineer

Working with Cadence design Systems on fpga based prototype system “Protium”. Around 20 yrs of experience primarily in the domain of fpga based Emulation, protyping, FPGA Design, Implementation on board, Timing Closure; having VHDL,verilog, Xilinx Vivado, ISE, Modelsim,VCS,synopsys tools, etc in my technological forte. --> Conduct research and development in HSV software, covering areas such as synthesis, front end and backend development, FPGA, debugging, power estimation, waveform reconstruction, and simulation. --> Contribute to the formulation and achievement of strategic software engineering goals --> Lead and drive progress in cross-functional projects and initiatives --> Develop sophisticated software code tailored to customer requirements --> Offer expert consultation for application development and design reviews across various organizations and architectures --> Innovate and provide crucial software advancements to enhance Protium’s performance. Protium stands as a leading product in the FPGA emulation and prototyping domain. Skills: --> Expertise in FPGA design, Implementation, STA (Timing Closure), Emulation, prototyping --> Expertise in Xilinx Vivado and ISE --> Emulation projects involving multiple FPGAs. --> Languages:VHDL, Verilog, SystemVerilog --> Tools: Cadence Protium, Xilinx Vivado, synopsys ZeBu, ISE, Timing Analyser, synplify pro, modelsim, VCS --> Basic understanding on verification methodologies, block level verification. Specialties: Cadence Protium, Synopsys ZeBu Emulation platform, FPGA Design, Implementation, compilation, STA, Timing Analysis, Xilinx FPGA and Tools

Stackforce AI infers this person is a specialist in FPGA design and emulation within the semiconductor industry.

Experience: 20 yrs 6 mos

Skills

Fpga Design
Prototyping
Emulation

Career Highlights

20 years of experience in FPGA design and emulation.
Expertise in Xilinx tools and FPGA-based prototyping.
Led cross-functional projects enhancing software engineering goals.

Work Experience

Cadence

SW Architect (6 mos)

SW Architect (1 yr 1 mo)

SW Architect (1 yr 8 mos)

Cirrus Logic

Implementation Engineer, Sr Staff - FPGA prototyping (2 yrs 9 mos)

Synopsys Inc

R&D, Staff - FPGA based Emulation at Synopsys (5 yrs 2 mos)

Xilinx

Sr. Software Engineer- Design & Analysis (5 yrs 3 mos)

HCL Technologies

Front end FPGA design/Prototyping (1 yr 4 mos)

Patni Computer Systems

Front end FPGA design (2 yrs 8 mos)

Education

P.G. Diploma at Centre for Development of Advanced Computing (C-DAC)

B.Tech at UP Technical University

Gaurav Kumar Srivastava

Software Engineer

United States20 yrs 6 mos experience

Highly Stable

Key Highlights

20 years of experience in FPGA design and emulation.
Expertise in Xilinx tools and FPGA-based prototyping.
Led cross-functional projects enhancing software engineering goals.

Stackforce AI infers this person is a specialist in FPGA design and emulation within the semiconductor industry.

Contact

Skills

Core Skills

Fpga DesignPrototypingEmulation

Other Skills

FPGAXilinx FPGAsLeadershipCross-functional Team LeadershipField-Programmable Gate Arrays (FPGA)Static Timing AnalysisTiming ClosureVerilogXilinx VivadoDebuggingTCLPlacement and Routing for FPGAsEDAZeBuFront end FPGA design

About

Experience

Cadence

3 roles

SW Architect

Sep 2025 – Present · 6 mos

SW Architect

Aug 2024 – Sep 2025 · 1 yr 1 mo

Working on FPGA based emulation and prototyping using Xilinx FPGAs.

FPGAXilinx FPGAsFPGA DesignPrototyping

SW Architect

Dec 2022 – Aug 2024 · 1 yr 8 mos

Working on FPGA based emulation and prototyping using Xilinx FPGAs.

EmulationPrototypingLeadershipCross-functional Team LeadershipField-Programmable Gate Arrays (FPGA)Static Timing Analysis+4

Cirrus logic

Implementation Engineer, Sr Staff - FPGA prototyping

Mar 2020 – Dec 2022 · 2 yrs 9 mos · Austin, Texas, United States

Worked with Audio Design Engineering group on FPGA prototyping/implementation.
RTL changes for FPGAs with considerations for memories, IO pads, gated clocks and complex generated clocks
Constraints definition for FPGAs
FPGA synthesis, place and route, timing analysis/optimizations using Xilinx Vivado
Work with cross functional teams on bringup, verification and debug
Flow automation and improvements for better compilability and reducing compile time

FPGADebuggingPrototypingStatic Timing AnalysisTCLPlacement and Routing for FPGAs+2

Synopsys inc

R&D, Staff - FPGA based Emulation at Synopsys

Dec 2014 – Feb 2020 · 5 yrs 2 mos · Mountain View, California

Worked on FPGA based emulation (ZeBu) using Xilinx FPGAs (V7 and Ultrascale).
Develop, analyze & optimize FPGA compilation methodologies for Synopsys proprietary ZeBu server emulation platforms.
P&R using Xilinx VIVADO, doing Static timing Analysis
Suggest RTL improvements to make the design FPGA friendly.
Perform QoR and routability analysis of customer designs and improve FPGA compilation flow.
FPGA P&R using Xilinx Vivado, doing Static timing Analysis
Drive analysis and adoption of advanced emulation specific features in latest generation of Xilinx UltraScale chips
Work on FPGA compilation for next gen zebu platform.
Waveform debugging and root cause/fix the compile/timing issues.
Interacting with Application Engineering team to deal with critical customer issues and proposing an overall solution to help compile successfully.
Collaborating with third party software vendor.

EmulationFPGAEDADebuggingPlacement and Routing for FPGAsStatic Timing Analysis+6

Xilinx

Sr. Software Engineer- Design & Analysis

Sep 2009 – Dec 2014 · 5 yrs 3 mos · Greater Hyderabad Area

Responsible for design specification and implementation for upcoming devices.
FPGA P&R using Xilinx Vivado, doing Static timing Analysis
RTL design and integration flow using Verilog and VHDL as coding language.
Design Analysis involving debugging timing failures and simulations of test suites.
Work with various teams (IP design, Emulation, etc) for design’s Timing Closure.
Identifying and categorizing design failures and methodology flow issues.
Update RTL for fixing the design failures and redirect flow related issues to tool development team.
Architecture evaluation and conducting experiments for design improvements
Fpga prototype