J

Jim Terence Colaço

Product Manager

Bengaluru, Karnataka, India10 yrs 9 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in end-to-end solution delivery in high-tech industries.
  • Proficient in PCIe and Ethernet protocols with hands-on design experience.
  • Strong leadership managing a team of engineers in ASIC design.
Stackforce AI infers this person is a highly skilled ASIC design manager with expertise in high-tech industries.

Contact

Skills

Core Skills

Project DeliveryComputer SimulationsMicroarchitectureRtl Design

Other Skills

CDCAltera Quartus IICommunicationFPGAAlgorithmsDigital ElectronicsDigital Signal ProcessorsVery-Large-Scale Integration (VLSI)MicrocontrollersShell ScriptingProgrammingCircuit DesignField-Programmable Gate Arrays (FPGA)VerilogVHDL

About

I manage a team of exceptional engineers. My technical expertise lies in the domains of writing specifications, building a micro-architecture, RTL design, Synthesis, Lint, CDC checks, DfT DRC, DfT architecture, DfT Insertion, STA and FPGA Design validation all in the scope IP level, Subsystem level and SoC level. I handle end to end solution delivery to customers in high tech industries like HPC, Consumer Electronics, and Automotive sectors. I’m adept at project management, delivering to multiple engagements on very challenging schedules. I am competent with DSP algorithms and blocks (Design and Implementation of filters, CORDIC and other useful blocks targeting DSP). I have in-depth knowledge of the PCIe protocol and hands on experience in building solutions using the same. I have also been responsible for developing an in-house PCIe IP and have designed and overlooked the design of PCIe Physical Layer with a small team of design and verification engineers at my previous organization. I am competent with the Ethernet protocol and have worked on adding features to an Ethernet Controller, MACSec implementation as well as integration of Ethernet controller and on-chip PHY. I have also had experience bringing up off-chip PHY ports with SFP interface via MDIO. I have hands on exposure and expertise with the PHY and MAC for PCIe and Ethernet use cases, having owned and designed the high speed interfaces subsystem for multiple products. I have an in-depth understanding of the ARM Cortex M7 processor, it’s capabilities and integration methodology. I am well versed with tools provided by Synopsys, Xilinx, Intel FPGA, Magillem, Mentor Graphics, and Cadence. I possess a very logical and rational mindset to tackle any problem. I also have excellent communication skills. When I'm not working I usually make music (I play the guitar) or enjoy a book. I also am a big fan of online gaming and enjoy long rides on my motorcycle. I would be happy to hear from you if you have a project I can help with or if my skills interest you.

Experience

Synopsys inc

2 roles

R&D Manager, ASIC Design

Promoted

Jan 2024Present · 2 yrs 2 mos

Project Delivery

Senior ASIC Design Engineer

Jan 2021Jan 2024 · 3 yrs

Computer SimulationsProject Delivery

Wipro limited

Senior VLSI Engineer (ASIC Design)

Nov 2018Dec 2020 · 2 yrs 1 mo · Bengaluru, Karnataka, India

MicroarchitectureCDC

A&w engineering works

FPGA Engineer

Feb 2017Nov 2018 · 1 yr 9 mos · Vadodara, Gujarat, India

Altera Quartus IIMicroarchitecture

Atria logic inc.

RTL Design Engineer

May 2015Feb 2017 · 1 yr 9 mos · Bangalore

RTL DesignComputer Simulations

Vector india pvt. ltd.

Embedded System Trainee

Oct 2014Apr 2015 · 6 mos · Bangalore

Education

Mangalore Institute of Technology and Engineering, Mangalore, India

Bachelor of Engineering (BE) — Electronics and Communications Engineering

Jan 2010Jan 2014

St. Joseph's Boys High School

Indian School Certificate Examination (ISC) — Science (Electronics)

Jan 2009Jan 2010

St. Joseph’s Boys’ High School

Indian Certificate of Secondary Education (ICSE)

Jan 2007Jan 2008

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