Jun 2019 – Nov 2020 · 1 yr 5 mos

• Responsible for Digital implementation including:
• Writing RTLs
• Timing constraints development from Scratch for multiple modes.
• RTL Synthesis and DFT Insertion.
• Formal Verification.
• Place and Route including following developments-
• Floor planning.
• Clock tree Synthesis and CTS constraints.
• Routing and Timing optimization.
• Static Timing Analysis
• Physical Verification including LVS, DRC, DFM, OPC, etc.
• Have Worked on 40nm, 28nm FDSOI and PCM based 28nm Nodes.

Feb 2019 – Jun 2019 · 4 mos

May 2018 – Jul 2018 · 2 mos · Noida Area, India

• Learnt different concepts of Verilog HDL, and it's coding uses.
• Learnt test bench generation using System Verilog. The major learnings are -
• SV OOPS
• SV Randomization
• SV Assertions (Immediate and Concurrent)
• SV Coverage (Functional and Code)
• Verified functionality for design of LC3 code.
• Learnt Basics of UVM.

Feb 2018 – May 2018 · 3 mos · Noida Area, India

• Learned about the Evolved Core of 4G LTE communication.
• Concepts different physical layers, establishing connections, data/voice transfer etc.
• Techniques to get better latency and data rate in 4G LTE.
• Verified drive test reports on TEMS Software and MapsInfo Professional.

Jun 2017 – Jul 2017 · 1 mo · Delhi

• Learnt concepts of Embedded Systems and PCB Fabrication
• Worked on Beagle Bone Black.
• Developed Ingenious Door Bell Solution -
• Using the concept of iot on beaglebone black designed an embedded system allowing the control of doorbell system through the telegram bot. Executed as a better security feature for common household.