Nov 2021 – Jun 2023 · 1 yr 7 mos

• Worked on Compute In-Memory (CIM) based accelerator design and system level analysis for various AR/VR workloads. This included new micro-architecture and dataflow design in RTL, SoC level design verification, working with different AR/VR product teams to map their workloads in the CIM based accelerator, simulator design (Python based) for energy and performance modeling with relevant CIM IPs to quickly explore a large design space for optimal hardware design, as well as evaluate the benefits of CIM at the system level.

Jun 2018 – Nov 2021 · 3 yrs 5 mos · Kilby Labs, Dallas

• Hardware/software co-design for low power neural network accelerators for edge-AI applications. Particular focus on in-memory computing approaches to address the limitations of traditional Von-Neumann digital architectures.
• Experienced in mixed-signal circuit design from transistor level all the way up to RTL level. Experienced in Static Random Access Memory (SRAM) design along with other key analog components including DACs, ADCs, PLLs etc..
• Experienced in RTL design of entire accelerator modules including datapath and full control logic in SoC/ASICs. Also experienced with FPGA implementation of system-level RTL designs for proof-of-concepts.
• Experienced in neural network training and modeling using PyTorch, MATLAB, C etc..

Jun 2017 – Jul 2017 · 1 mo · Grenoble Area, France

Jun 2015 – Aug 2015 · 2 mos

Sep 2012 – May 2018 · 5 yrs 8 mos

• Pursued PhD, dissertation: "Energy-Efficient Smart Embedded Memory Design for IoT and AI".
• Worked on high-throughput and energy-efficient SRAMs with in-memory computation capability for low-power, real-time machine learning applications, under the guidance of Prof. Anantha Chandrakasan. Developed and demonstrated on silicon (65nm CMOS), a compute in-memory SRAM array which can run massively parallel dot-products for neural networks, in a highly energy-efficient manner (published at ISSSCC 2018, JSSC 2019).