Anandhan M

CEO

Bengaluru, Karnataka, India19 yrs 3 mos experience

Highly Stable

Key Highlights

Expert in Low-power ASIC design and implementation.
Proficient in RTL design and integration methodologies.
Experienced in Static Timing Analysis and Formal Verification.

Stackforce AI infers this person is a Low-power ASIC Design Engineer with extensive experience in VLSI.

Contact

Skills

Core Skills

Low-power Design

Other Skills

SynthesisSTAECOPtPxPowerArtistUPFSoCVLSIVerilogASICLogic SynthesisCLPStatic Timing AnalysisConformal LECCDC

About

ASIC RTL Design Implementation engineer with experience in - RTL Design and Integration - CLP (Low Power) Check with UPF - Low Power Design (multi voltage, power domain, etc) - CDC-Check, Lint-Check - Synthesis (Design Compiler, Fusion Compiler) - STA (primetime) - Formal Verification (LEC) - RTL Power Analysis (PowerArtist) - Netlist Power Extraction (PtPx -PrimetimePX) - Power Modelling - ECO, Conformal ECO - DDR LP4/LP5 Subsystems - Display Subsystems

Experience

19 yrs 3 mos

Total Experience

3 yrs 6 mos

Average Tenure

1 yr 9 mos

Current Experience

Amd

Sr. Manager

Jul 2024 – Present · 1 yr 9 mos · Bengaluru, Karnataka, India · On-site

Qualcomm

2 roles

Senior Staff Engineer

Promoted

Dec 2019 – Jul 2024 · 4 yrs 7 mos

Low-power Design

Staff Engineer

May 2016 – Dec 2019 · 3 yrs 7 mos

Working on IP level Design and Synthesis/STA/ECO and PtPx/PowerArtist and LowPower/UPF.

Low-power DesignSynthesisSTAECOPtPxPowerArtist+1

Mts, mirafra technologies

3 roles

Consultant@ Qualcomm

May 2015 – Apr 2016 · 11 mos

Working on IP level Design and Synthesis

Low-power Design

Consultant@ Qualcomm

Feb 2013 – Apr 2015 · 2 yrs 2 mos

Working on IP level Design and Synthesis.

Low-power Design

Consultant@ Texas Instruments

Dec 2011 – Jan 2013 · 1 yr 1 mo

Worked on SoC level Design and Integration in WBU-TI

Senior engineer, l&t infotech

2 roles

Consultant@ Qualcomm

Aug 2011 – Dec 2011 · 4 mos

Consultant@ Intel Mobile Communications

Aug 2010 – Jul 2011 · 11 mos

Asic engineer, soctronics

Consultant@ AMD

Jun 2009 – Aug 2010 · 1 yr 2 mos · Greater Hyderabad Area

Digibee microsystems

Member Technical Staff

May 2006 – Feb 2009 · 2 yrs 9 mos · Greater Chennai Area

Education

Anna University Chennai

M.E — Communication Systems

Jan 2004 – Jan 2006

THANTHAI PERIYAR GOVERNMENT INSTITUTE OF TECHNOLOGY

BE — ECE

Jan 2000 – Jan 2004

Stackforce found 100+ more professionals with Low-power Design

Explore similar profiles based on matching skills and experience

Sreekanth Mapu

Staff Engineer

at Qualcomm

Bengaluru, India12 yrs 1 mo exp

Physical DesignStatic Timing AnalysisClock Tree Synthesis

Dravit Rana

Physical Design Senior Staff Engineer

at MediaTek

Bengaluru, India12 yrs 4 mos exp

Physical DesignPower Integrity

Himanshu Singh

DFT Engineer

at AMD

India12 yrs 11 mos exp

DFTSilicon debug

Aniket Joshi

Staff Engineer

at MediaTek

Bengaluru, India6 yrs 9 mos exp

Physical DesignStatic Timing Analysis

SHWETHA RS

System-on-Chip Design Engineer

at Intel Corporation

Bengaluru, India6 yrs 10 mos exp

Logic SynthesisStatic Timing Analysis

Somya Dashora

Staff Engineer

at Qualcomm

Udaipur, India7 yrs 4 mos exp

CPU designVirtualizationSystem Verilog

Vikas Verma

Senior Staff Engineer

at MediaTek

Bengaluru, India13 yrs 5 mos exp

VLSISoCPhysical DesignTiming Closure

Raj Godara

Sr. Silicon Design Engineer

at AMD

Hyderabad, India3 yrs 8 mos exp