Rahul Kataria

Software Engineer

Bengaluru, Karnataka, India11 yrs 9 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expertise in low power architecture and methodologies.
Proven track record in ASIC design and physical design.
Strong background in RTL design and verification.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC and VLSI methodologies.

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Skills

Core Skills

Asic DesignPhysical DesignRtl Design

Other Skills

Standard Cell Library BenchmarkingPlace and Route Methodology DefinitionPPA EvaluationCongestion AnalysisASIC physical design flowsRTL design and VerificationGDS ImplementationPost Silicon ValidationLayout Architecture DefinitionASIC Design ImplementationMemory BISTPerformance AnalysisCVerilogC++

About

I have done my bachelors from IIT Kanpur and have a keen interest in VLSI. Working as Low Power Architect and Methodology Engineer in the ASIC Team Defining low power architecture and developing methodology for techniques like Multi-Voltage Islands and Power Gating for FX14/FX7 FinFET technologies Working with customers on early engagement for power reduction and thermal mitigation techniques Developing methodology for power reduction techniques during synthesis, timing and sign-off stages Netlist power optimization using various features of Primetime PX tools. I have experience in standard cell library benchmarking and test chip team which involves block level PPA analysis of libraries and development of physical design methodologies to achieve PPA targets. Experience in extraction of design parameters, QoR metrics and analyzing trends. I have worked across different aspects of chip manufacturing - from RTL , Design Verification,Physical Design Implementation, Static Timing Analysis, IR Drop Analysis, Circuit Design and Clock and Power Management. I like to utilize my skills in resolving new challenges and come up with a solution which keeps my learning curve up and helps in designing good IP’s.

Experience

11 yrs 9 mos

Total Experience

3 yrs 11 mos

Average Tenure

6 yrs 11 mos

Current Experience

Marvell technology

2 roles

Senior Staff Engineer

Promoted

Apr 2022 – Present · 4 yrs 1 mo

Staff Engineer Physical Design

Jun 2019 – Apr 2022 · 2 yrs 10 mos

Samsung electronics

2 roles

Associate Staff Engineer

Mar 2018 – May 2019 · 1 yr 2 mos · Bengaluru Area, India

Standard Cell Library Benchmarking
Place and Route Methodology Definition and Improvement
PPA Evaluation of Standard Cell Libraries using ICC, ICC2 flows.
Congestion Analysis and Solutions
Standard Cell Design and Benchmarking.
Experience in extraction of design parameters, QoR metrics and analyzing trends.
Experience in ASIC physical design flows and methodologies in 7nm-40nm process nodes.
Experience in ASIC physical design, digital design and physical design flows (synthesis, place and route( ICC and ICC2), STA, DFT, formal verification, CDC, and power analysis, IR/EM analysis).
Test Chip Design Team:
Carried out Test Chip implementation from RTL to GDS to post silicon validation for various nodes from 10 to 100nm.
Experience in IP integration (memories, FLASH, IO’s and Analog IP).
Experience in RTL design and Verification.

Standard Cell Library BenchmarkingPlace and Route Methodology DefinitionPPA EvaluationCongestion AnalysisASIC physical design flowsRTL design and Verification+2

Senior Hardware Engineer

Apr 2016 – Feb 2018 · 1 yr 10 mos · Bengaluru Area, India

Standard Cell Library Benchmarking and Test Chip Development.
Place and Route Methodology Definition and Improvement
PPA Evaluation of Standard Cell Libraries using ICC, ICC2 flows.
Congestion Analysis and Solutions
Standard Cell Design and Benchmarking.
Test Chip Design and Implementation
Layout Architecture Definition, Layout Quality Analysis, Bench-marking of ARM Cores
LEF and Milkyway generation and Validation(10nm, 28nm,32nm,65nm, 90 nm, 135nm)
Design Automation, Flow Development and Support using Perl & TCL scripting
Mentoring, Project Planning and Tracking, Collaborating with different teams
Excellent verbal and written communication skill

Standard Cell Library BenchmarkingPlace and Route Methodology DefinitionPPA EvaluationCongestion AnalysisLayout Architecture DefinitionPhysical Design+1

Qualcomm

3 roles

Associate Engineer

Jul 2014 – Apr 2016 · 1 yr 9 mos

I was involved in a rotation program and worked in RTL Design, ASIC Design Implementation and MBIST team.
WIRELESS LAN DESIGN (RTL Design Team): July 2014-January 2015
Implementation of NoC ( Network on Chip) Architecture. Performance Analysis of NoC.
Execution of PLDRC, CDC( Clock Domain Crossing) and CLP ( Conformal Low Power flow).
ASIC SoC Physical Design Implementation: January 2015-May2015
Implemented physical design of macro in the chip. Carried out placement, routing of cells inside the macro to meet the required timing closure for the block.
Learned different tools and flows like : Olympus, FE(First Encounter), ICC ,STARXT.
Memory BIST( Built-In Self Test) : May2015-Sept2015
Carried out Memory testing in a project. Learnt Different Memory Test Algorithms. Carried out simulations in MODELSIM and VCS Environment.

RTL DesignASIC Design ImplementationMemory BISTPerformance AnalysisASIC Design

Associate Engineer

Jun 2014 – Apr 2016 · 1 yr 10 mos

Intern

May 2013 – Jul 2013 · 2 mos · Bengaluru Area, India

MODEM DESIGN TEAM :
Worked on optimization of MODEM filters.
Implemented modem filters with using the negative edge of clock to reduce multipliers and in turn reduce chip area.