VANAJA G U

Software Engineer

Bengaluru, Karnataka, India5 yrs 7 mos experience

Highly Stable

Key Highlights

Expert in Cadence SKILL and layout design.
Led multiple projects across various technology nodes.
Strong background in semiconductor engineering.

Stackforce AI infers this person is a Semiconductor Engineering Specialist with expertise in layout design and process integration.

Contact

Skills

Core Skills

Layout DesignCadence Skill

Other Skills

Design Rule Checking (DRC)Cadence VirtuosoCalibreParametrized Pcell using SKILLCadence Mask ComposeKshSVRFCalibreDRVTCLMATLABC (Programming Language)Open Source PlatformsAdobe Acrobat

About

Has exposure in generating Parameterized Cells using Cadence SKILL. Worked on different technology nodes from 45nm-350nm and developed electrical and optical contents for reticle frames. Tools: Cadence Virtuoso, Quickview (K2 Viewer), Mask Compose, Calibre DRV, Calibre RVE Languages/Scripting: Cadence SKILL, SVRF, Calibre DRV, TCL, KSH

Experience

Infineon technologies

Staff Engineer

Aug 2025 – Present · 7 mos · India

Globalfoundries

3 roles

Principal Frame Engineer

Promoted

Jul 2024 – Sep 2025 · 1 yr 2 mos

Layout Design:
Lead the TD test chip development and qualification projects for 12nm, 14nm, 22nm, 45nm, 90nm, 130nm, 180nm tech nodes for existing and new technologies as per Fab and customer requirements.
Engaged with Technology Development, Process Integration, Metrology, Photolithography, Characterization, Data preparation, Design Services, OPC and Mask House teams to develop electrical and optical macro layouts.
Supported manual and automated layout generation using Cadence SKILL and Calibre for scribe line electrical layouts, lithography structures.
Lead the projects for homogeneous and heterogenous 3D wafer to wafer bonding for lower tech nodes.
Layout support for technology transfers and one common frame convergence for multiple Fabs.

Design Rule Checking (DRC)Cadence VirtuosoLayout DesignCadence SKILL

Senior Frame Engineer

Jul 2020 – Jun 2024 · 3 yrs 11 mos

Layout Design:
Lead the TD test chip development and qualification projects for 12nm, 14nm, 22nm, 45nm, 90nm, 130nm, 180nm tech nodes for existing and new technologies as per Fab and customer requirements.
Engaged with Technology Development, Process Integration, Metrology, Photolithography, Characterization, Data preparation, Design Services, OPC and Mask House teams to develop electrical and optical macro layouts.
Supported manual and automated layout generation using Cadence SKILL and Calibre for scribe line electrical layouts, lithography structures.
Lead the projects for homogeneous and heterogenous 3D wafer to wafer bonding for lower tech nodes.
Layout support for technology transfers and one common frame convergence for multiple Fabs.
Floor Planning:
Developed flow for reticle and wafer floor planning for tape-outs as per customer requirements.
Trained in and completed Frame generation for various technologies.

Design Rule Checking (DRC)Cadence VirtuosoLayout DesignCadence SKILL

Intern

Feb 2020 – Jul 2020 · 5 mos

Design Rule Checking (DRC)

Nxp semiconductors

Intern

Jun 2019 – Feb 2020 · 8 mos · India

System level modelling using open-source ISA (RISC-V)
Design and Development of Open-core virtual SoC Platform for DSP applications
To develop the virtual prototype of the SoC by configuring different open core CPUs using IMPERAS
Professional Tool and to analyze its performance.
Profiling And Performance Analysis of Benchmark Applications Using RISC-V Processor
To develop and simulate the DSP application using IMPERAS Professional tool.
Analyze the performance of various RISC-V Variants
Comparison of RISC-V performance with ARM Cortex-M4