Vishakh V Bharadwaj

CEO

Bengaluru, Karnataka, India10 yrs 1 mo experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Analog Mixed Signal layout design.
Proficient in multiple technology nodes including 3nm and 5nm.
Strong communication skills with design teams.

Stackforce AI infers this person is a Semiconductor layout design expert with extensive experience in Analog Mixed Signal technologies.

Contact

vishakh169@gmail.com LinkedIn

Skills

Core Skills

Analog Layout DesignVlsi

Other Skills

CC++CAD activitiesCMOSCMOS process technologiesCalibreCustomer ServiceDLLDesign Rule Checking (DRC)EnglishFINFET technologyFIVRHTMLIO layout designLayout Design

About

Core Competency • Capable of designing full custom analog/IO layout from given schematics/netlist • Worked on various process nodes, Intel (14nm, 10nm and 7nm), SMIC 40nm, TSMC (28nm, 22nm, 7nm, 5nm and 3nm) • Additional skill in CAD related work – Tool validation & testing utilities used in layout • Understanding user perspective while using tools for layout building and providing feedback for a better user experience & increased productivity • Analog Mixed Signal layout design work for core components in PLL, regulators, I/O’s, BGR • Floor planning, applying matching techniques for analog layouts like OPAMP • Post layout verification DRC, LVS, density checks, ERC • Electrical aware designs in lower technology nodes, paracitic reduction • Good communication skills to interact with designers, understand & build layouts as per requirement • Experience in handling ECO changes, antenna, latch-up rules, HV violations, reliability verification

Experience

Cadence design systems

Lead Engineer

Oct 2022 – Present · 3 yrs 5 mos · Bengaluru, Karnataka, India · Remote

Leadic design pvt ltd

Senior Analog layout design engineer

Apr 2021 – Aug 2022 · 1 yr 4 mos · Bengaluru, Karnataka, India

IO layout design, Analog layout design and CAD activities - Worked on tech nodes TSMC 7nm, 28nm

IO layout designAnalog layout designCAD activitiesVLSI

Altran

Analog Layout Design Engineer

Sep 2017 – Apr 2021 · 3 yrs 7 mos · Bengaluru, Karnataka, India

Projects worked on PLL, FIVR, MDIO, DLL
Worked on layout design projects in FINFET 3nm, 5nm, 7nm, 10nm & 14nm technology nodes.
Closely worked with clients, leads, design engineers, design automation teams.

PLLFIVRMDIODLLlayout designFINFET technology+2

Rv-vlsi vlsi and embedded systems design center

Analog layout Design Engineer Trainee

Mar 2017 – Sep 2017 · 6 mos · Bengaluru, Karnataka, India

Worked on layout design of standard cells, analog and memory design involving full custom layout flow
Proficient in physical verification (DRC, LVS)
CMOS process technologies: 28nm, 90nm, 180nm
Used tools: Pyxis (icstudio) from Mentor Graphics, Calibre
Learnt scripting languages: Shell and perl

layout designphysical verificationCMOS process technologiesscripting languagesAnalog layout designVLSI

Convergys

Microsoft Technical Support Engineer

Oct 2015 – Dec 2016 · 1 yr 2 mos · Bengaluru, Karnataka, India

Technical support associate for Microsoft process, involving online live chat, troubleshooting Windows OS and MS Office and resolution of all technical issues
Proficient in providing level 1 technical support to end-users
Experience in installation of Windows, configuration, technical troubleshooting, diagnosing hardware and software problems using various Microsoft tools
Microsoft Office, Outlook configuration, activation and troubleshooting on Windows and Mac platforms

technical supportWindows OSMS Office