Manikandan Palanisamy

Software Engineer

Bengaluru, Karnataka, India12 yrs 9 mos experience

Highly Stable

Key Highlights

12 years of experience in DFT implementation.
Expertise in multi-core processor tape-outs.
Strong skills in RTL design and formal verification.

Stackforce AI infers this person is a Semiconductor Engineering expert with a focus on DFT and RTL design.

Contact

Skills

Core Skills

DftRtl Design

Other Skills

Formality VerificationDFT and DFD tasksAutomating DFT tasksCCore JAVAVerilogSystem VerilogPerlMakefileTCLDigital ElectronicsMicrocontrollersVHDLXilinxMicroprocessors

About

 ~12 years of professional experience, mostly focused on DFT implementation and post silicon bring-up.  Self-motivated /quick learner who always looks forward to learn and improve.  Wide range of tape-outs from Samsung Exynos processors, multi-core Intel server chips, Qualcomm snapdragon processors; From 2nm technology to flat-design (single core) microcontroller chips of 160nm technology.  Looking for challenging opportunities through which I can learn and nurture my DFT/leadership skills to add value to my team/organization Area of Interest: DFT , Post Silicon Bringup, RTL Design , Formality Verification, Digital Electronics, Control systems, Embedded Systems, Software Systems, Tools Worked : DFT Tools for Boundary Scan and Memory BIST insertion (Mentor Tessent) , Mentor TestKompress and FastScan for ATPG, Lauterbach Trace 32, Load Runner,QuestaSim, VCS , Verdi Programming Languages: C, Core JAVA, Verilog, System Verilog Scripting Languages: Perl , Makefile , TCL.

Experience

Nvidia

Senior ASIC Engineer

Sep 2025 – Present · 6 mos

Samsung semiconductor india

Senior Staff Engineer

May 2023 – Sep 2025 · 2 yrs 4 mos

Intel corporation

DFT Engineer

May 2019 – May 2023 · 4 yrs · Bengaluru Area, India

Qualcomm

Senior Engineer

Jul 2016 – May 2019 · 2 yrs 10 mos · Bangalore

Microchip technology

Engineer 1 - Design

Apr 2014 – May 2016 · 2 yrs 1 mo · Chennai Area, India

Working for UNG (USB and Networking Group) division of Microchip Technology Inc.
So far Involved in two tapeouts,
1). USB3.0 HUB
2). USB3.0 HUB with TYPE -C connector support.
RTL design for OTP (One Time Programmable) controller block.
Automating DFT tasks using Makefile scripting and Perl scripting
Formality Verification
DFT and DFD tasks such as 'LV Flow ownership' for inserting boundary scan and Memory BIST logic ; ATPG Pattern generation , verification and 'Burn_In' test mode creation.

DFTFormality VerificationDFT and DFD tasksAutomating DFT tasksRTL designRTL Design

Cognizant technology solutions

Programmer Analyst Trainee

Aug 2013 – Apr 2014 · 8 mos · Chennai Area, India

Worked on Banking and Financial Software products performance testing using Load Runner tool.
Client : Lloyds Banking Group, UK.

Stmicroelectronics

Intern

Jan 2013 – May 2013 · 4 mos · Greater Noida,India

Part of Post silicon functional validation team which is responsible for validating 32 bit micro controller designed for automotive applications.

Isro

Trainee

May 2012 – Jun 2012 · 1 mo · Trivandrum

Developed a 16 bit low power microprocessor which can be used for low speed signal processing applications such as ticket printing. VHDL was the language used and OrCAD was the simulation tool used.